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octal lna/vga/aaf/adc and crosspoint switch preliminary technical data AD9271 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features 8 channels of lna, vga, aaf, and adc low noise preamplifier (lna) input-referred noise = 1.2 nv/hz @ 7.5 mhz typical spi-programmable gain = 14 db/15.6 db/18 db single-ended input; v in maximum = 400 mv p-p/ 333 mv p-p/250 mv p-p dual mode, active input impedance match bandwidth (bw) > 70 mhz full-scale (fs) output = 2 v p-p diff variable gain amplifier (vga) gain range = ?6 db to +24 db linear-in-db gain control antialiasing filter (aaf) 3 rd -order butterworth cutoff programmable from 8 mhz to 18 mhz analog-to-digital converter (adc) 12 bits at 10 msps to 50 msps snr = 70 db sfdr = 80 db serial lvds (ansi-644, ieee 1596.3 reduced range link) data and frame clock outputs includes crosspoint switch to support continuous wave (cw) doppler low power, 150 mw/channel at 12 bits/40 msps (tgc) 60 mw/channel in cw doppler single 1.8 v supply (3.3 v supply for cw doppler output bias) flexible power-down modes overload recovery in <10 ns fast recovery from low power standby mode, <2 s 100-pin tqfp applications medical imaging/ultrasound automotive radar general description the AD9271 is designed for low cost, low power, small size, and ease of use. it contains eight channels of a variable gain amplifier (vga) with low noise preamplifier (lna); an antialiasing filter (aaf); and a 12-bit, 10 msps to 50 msps analog-to-digital converter (adc). each channel features a variable gain range of 30 db, a fully differential signal path, an active input preamplifier termination, a maximum gain of up to 40 db, and an adc with a conversion rate of up to 50 msps. the channel is optimized for dynamic performance and low power in applications where a small package size is critical. the lna has a single-ended-to-differential gain that is selectable through the spi. the lna input noise is typically 1.2 nv/hz, functional block diagram serial port interface reference fco+ fco? dco+ dco? lna losw-h lo-h li-h lg-h 12-bit pipeline adc serial lvds dout + h dout ? h lna lo-g losw-g li-g lg-g 12-bit pipeline adc serial lvds dout + g dout ? g lna lo-f losw-f li-f lg-f 12-bit pipeline adc serial lvds dout + f dout ? f lna lo-e losw-e li-e lg-e 12-bit pipeline adc serial lvds dout + e dout ? e lna lo-d losw-d li-d lg-d 12-bit pipeline adc serial lvds dout + d dout ? d lna lo-c losw-c li-c lg-c 12-bit pipeline adc serial lvds dout + c dout ? c lna lo-b losw-b li-b lg-b 12-bit pipeline adc serial lvds dout + b dout ? b lna lo-a losw-a li-a lg-a 12-bit pipeline adc serial lvds dout + a dout ? a avdd stdby drvdd pwdn clk ? clk + sdio sclk csb rbias reft refb vref sense gain+ gain? cwd+/?[5:0] cwvdd switch array data rate multiplier 06304-001 aaf aaf aaf aaf aaf aaf aaf aaf AD9271 vga vga vga vga vga vga vga vga g m 6 figure 1.block diagram and the combined input-referred noise of the entire channel is 1.4 nv/hz at maximum gain. assuming a 15 mhz noise bandwidth (nbw) and a 15.6 db lna gain, the input snr is roughly 86 db. in cw doppler mode, the lna output drives a transconductance amp that is switched through an 8 6, differential crosspoint switch. the switch is programmable through the spi.
AD9271 preliminary technical data rev. pra | page 2 of 58 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 product highlights ........................................................................... 3 specifications..................................................................................... 4 ac specifications.......................................................................... 4 digital specifications ................................................................... 8 switching specifications .............................................................. 9 adc timing diagrams ................................................................. 10 absolute maximum ratings.......................................................... 11 thermal impedance ................................................................... 11 esd caution................................................................................ 11 pin configuration and function descriptions........................... 12 equivalent circuits ......................................................................... 15 typical performance characteristics ........................................... 17 theory of operation ...................................................................... 20 ultrasound................................................................................... 20 channel overview...................................................................... 21 input overdrive .......................................................................... 23 cw doppler operation............................................................. 23 tgc operation........................................................................... 25 a/d converter ............................................................................ 28 clock input considerations...................................................... 28 serial port interface (spi).............................................................. 35 hardware interface..................................................................... 35 memory map .................................................................................. 37 reading the memory map table.............................................. 37 reserved locations .................................................................... 37 default values ............................................................................. 37 logic levels................................................................................. 37 evaluation board ............................................................................ 42 power supplies ............................................................................ 42 input signals................................................................................ 42 output signals ............................................................................ 42 default operation and jumper selection settings................. 43 outline dimensions ....................................................................... 56 ordering guide .......................................................................... 56 revision history x/07revision 0: initial version
preliminary technical data AD9271 rev. pra | page 3 of 58 the AD9271 requires a lvpecl-/cmos-/lvds-compatible sample rate clock for full performance operation. no external reference or driver components are required for many applications. the adc automatically multiplies the sample rate clock for the appropriate lvds serial data rate. a data clock (dco) for capturing data on the output and a frame clock (fco) trigger for signaling a new output byte are provided. powering down individual channel is supported to increase battery life for portable applications. there is also a standby mode option that allows quick power-up for power cycling. in cw doppler operation, the vga, aaf, and adc are powered down. the power of the tgc path scales with selectable speed grades. the adc contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. the digital test patterns include built-in fixed patterns, built-in pseudorandom pattern, and custom user-defined test patterns entered via the serial port interface. fabricated in an advanced cmos process, the AD9271 is available in a 14 mm 14 mm, pb-free, 100-lead tqfp. it is specified over the industrial temperature range of C40c to +85c. product highlights 1. small footprint. eight channels are contained in a small, space-saving package. full tgc path, adc, and crosspoint switch contained within a 100-lead, 16 mm 16 mm, tqfp. 2. low power of 150 mw/channel at 40 msps. 3. integrated crosspoint switch. this switch allows numerous multichannel configuration options to enable the cw doppler mode. 4. ease of use. a data clock output (dco) operates up to 300 mhz and supports double data rate operation (ddr). 5. user flexibility. serial port interface (spi) control offers a wide range of flexible features to meet specific system requirements. 6. integrated third-order antialiasing filter. this filter is placed between tgc path and adc and is programmable from 8 mhz to 18 mhz.
AD9271 preliminary technical data rev. pra | page 4 of 58 specifications ac specifications avdd = 1.8 v, drvdd = 1.8 v, cwvdd = 3.3 v, 1.0 v internal adc reference, ain = 5 mhz, r s = 50 , lna gain = 15.6 db (6), unless otherwise noted. table 1. AD9271-25 AD9271-40 AD9271-50 parameter 1 conditions min typ max min typ max min typ max unit lna characteristics gain = 5/6/8 single-ended input to differential output 14/15.6/18 14/15.6/18 14/15.6/18 db single-ended input to single-ended output 8/9.6/12 8/9.6/ 12 8/9.6/12 db input voltage range, gain = 5/6/8 lna output limited to 2 v p-p differential output 400/333/250 400/333/250 400/333/250 mv p-p se 2 input common mode 1.4 1.4 1.4 v input resistance rfb = 200 , 50 50 50 rfb = 400 , 100 100 100 rfb = 15 15 15 k input capacitance li-x 15 15 15 pf ?3 db bandwidth 40 60 70 mhz input noise voltage, gain = 5/6/8 r s = 0 , rfb = 1.4/1.4/1.3 1.3/1.2/1. 1 1.3/1.2/1.1 nv/hz 1 db input compression point gain = 5/6/8 v gain = 0 v 782.6/649.1/508.8 782.6/649. 1/508.8 782.6/649.1/508.8 mv p-p active termination match , rfb = 200 6.7 6.7 6.7 db unterminated rfb = 4.9 4.4 4.2 db full-channel (tgc) characteristics aaf high-pass cutoff ?3 db dc/350/700 dc/ 350/700 dc/350/700 khz aaf low-pass cutoff ?3 db, programmable 1/3 f sample (8 to 18) 1/3 f sample (8 to 18) 1/3 f sample (8 to 18) mhz group delay variation f = 1 mhz to 10 mhz, gain = 0 v to 1 v 1 1 1 ns bandwidth tolerance 15 15 15 % input-referred noise voltage, lna gain = 5/6/8 rfb = 1.7/1.6/1.5 1.6/1. 4/1.3 1.6/1.4/1.2 nv/hz correlated noise no signal ?30 ?30 ?30 db output offset aaf high-pass = 700 khz tbd tbd tbd lsb signal-to-noise ratio (snr) f in = 5 mhz at ?7 dbfs gain pin = 0 v 65 65 65 dbfs
preliminary technical data AD9271 rev. pra | page 5 of 58 AD9271-25 AD9271-40 AD9271-50 parameter 1 conditions min typ max min typ max min typ max unit f in = 5 mhz at ?1 dbfs gain pin = 1 v 65 65 65 dbfs harmonic distortion second harmonic, f in = 5 mhz at ?7 dbfs gain pin = 0 v ?65 ?65 ?65 dbfs second harmonic, f in = 5 mhz at ?1 dbfs gain pin = 1 v ?65 ?65 ?65 dbfs third harmonic, f in = 5 mhz at ?7 dbfs gain pin = 0 v ?70 ?70 ?70 dbfs third harmonic, f in = 5 mhz at ?1 dbfs gain pin = 1 v ?70 ?70 ?70 dbfs two-tone imd3 (2 f1 ? f2) distortion f in1 = 5.0 mhz at ?1 dbfs f in2 = 5.1 mhz at ?26 dbfs gain pin = 1 v ?65 ?65 ?65 db channel-to- channel crosstalk ?70 ?70 ?70 db channel-to- channel crosstalk (overrange condition) 3 ?70 ?70 ?70 db overload recovery lna or vga 10 10 10 ns gain accuracy absolute gain error 0 < v gain < 0.1 v ?1.0 +0.5 +2.0 ?1.0 +0.5 +2.0 ?1.0 +0.5 +2.0 db 0.1 v < v gain < 0.9 v, 1 ?1.0 + 0.3 +1.0 ?1.0 + 0.3 +1.0 ?1.0 + 0.3 +1.0 db 0.9 v < v gain < 1 v ?2.0 -0.5 +1.0 ?2.0 -0.5 +1.0 ?2.0 -0.5 +1.0 db channel-to- channel matching 0.1 v < v gain < 0.9 v 1 1 1 db gain control interface normal operating range 0 1 0 1 0 1 v gain range 0 v to 1 v 10.6 40.6 10.6 40.6 10.6 40.6 db scale factor 32 32 32 db/v response time 30 db change 350 350 350 ns cw doppler mode transconductance, lna gain = 5/6/8 10/12/16 10/12/16 10/12/16 ma/v common mode cw doppler output pins 1.5 3.6 1.5 3.6 1.5 3.6 v input-referred noise voltage, lna gain = 5/6/8 r s = 0 , rfb = 1.8 /1.7/1.5 1.7 /1.5/1.4 1.7 /1.5/1.3 nv/hz output dc bias per channel 2.4 2.4 2.4 ma maximum output swing per channel 2 2 2 ma p- p power supply avdd 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v
AD9271 preliminary technical data rev. pra | page 6 of 58 AD9271-25 AD9271-40 AD9271-50 parameter 1 conditions min typ max min typ max min typ max unit drvdd 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v cwvdd 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 i avdd full-channel mode 500 622 746 ma cw doppler mode with four channels enabled 136 160 170 ma i drvdd 49 49 49 ma total power dissipation (including output drivers) full-channel mode 984 1200 1400 mw cw doppler mode with four channels enabled 192 216 224 mw power-down dissipation 10 mw standby power dissipation 65 65 65 mw power supply rejection ratio (psrr) 1 1 1 mv/v adc resolution 12 12 12 bits
preliminary technical data AD9271 rev. pra | page 7 of 58 AD9271-25 AD9271-40 AD9271-50 parameter 1 conditions min typ max min typ max min typ max unit adc reference output voltage error (vref = 1 v) 2 2 2 mv load regulation @ 1.0 ma (vref = 1 v) 3 3 3 mv input resistance 6 6 6 k 1 see the an-835 application note , understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. 2 se = single ended. 3 the overrange condition is specified as being 6 db more than the full-scale input range.
AD9271 preliminary technical data rev. pra | page 8 of 58 digital specifications avdd = 1.8 v, drvdd = 1.8 v, cwvdd = 3.3 v, 400 m v p-p differential input, 1.0 v internal adc reference, ain = ?0.5 dbfs, unle ss otherwise noted. table 2. parameter 1 temperature min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl differential input voltage 2 full 250 mv p-p input common-mode voltage full 1.2 v input resistance (differential) 25c 20 k input capacitance 25c 1.5 pf logic inputs (pdwn, stby, sclk) logic 1 voltage full 1.2 3.6 v logic 0 voltage full 0.3 v input resistance 25c 30 k input capacitance 25c 0.5 pf logic input (csb) logic 1 voltage full 1.2 3.6 v logic 0 voltage full 0.3 v input resistance 25c 70 k input capacitance 25c 0.5 pf logic input (sdio) logic 1 voltage full 1.2 drvdd + 0.3 v logic 0 voltage full 0 0.3 v input resistance 25c 30 k input capacitance 25c 2 pf logic output (sdio) 3 logic 1 voltage (i oh = 800 a) full 1.79 v logic 0 voltage (i ol = 50 a) full 0.05 v digital outputs (d+, d?), (ansi-644) 1 logic compliance lvds differential output voltage (v od ) full 247 454 mv output offset voltage (v os ) full 1.125 1.375 v output coding (default) offset binary digital outputs (d+, d?), (low power, reduced signal option) 1 logic compliance lvds differential output voltage (v od ) full 150 250 mv output offset voltage (v os ) full 1.10 1.30 v output coding (default) offset binary 1 see the an-835 application note , understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. 2 specified for lvds and lvpecl only. 3 specified for 13 sdio pins sharing the same connection.
preliminary technical data AD9271 rev. pra | page 9 of 58 switching specifications avdd = 1.8 v, drvdd = 1.8 v, cwvdd = 3.3 v, 400 m v p-p differential input, 1.0 v internal adc reference, ain = ?0.5 dbfs, unle ss otherwise noted. table 3. parameter 1 temp min typ max unit clock 2 maximum clock rate full 50 msps minimum clock rate full 10 msps clock pulse width high (t eh ) full 10.0 ns clock pulse width low (t el ) full 10.0 ns output parameters 2, 3 propagation delay (t pd ) full 1.5 2.3 3.1 ns rise time (t r ) (20% to 80%) full 300 ps fall time (t f ) (20% to 80%) full 300 ps fco propagation delay (t fco ) full 1.5 2.3 3.1 ns dco propagation delay (t cpd ) 4 full t fco + (t sample /24) ns dco to data delay (t data ) 4 full (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 ps dco to fco delay (t frame ) 4 full (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 ps data-to-data skew (t data-max ? t data-min ) full 50 200 ps wake-up time (standby) 25c 600 ns wake-up time (power-down) 25c 375 s pipeline latency full 8 clk cycles aperture aperture uncertainty (jitter) 25c <1 ps rms 1 see the an-835 application note , understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. 2 can be adjusted via the spi interface. 3 measurements were made using a part soldered to fr4 material. 4 t sample /24 is based on the number of bits divided by 2, because the delays are based on half duty cycles.
AD9271 preliminary technical data rev. pra | page 10 of 58 adc timing diagrams dco? dco+ dout? dout+ fco? fco+ ain clk? clk+ msb n ? 8 d10 n ? 8 d9 n ? 8 d8 n ? 8 d7 n ? 8 d6 n ? 8 d5 n ? 8 d4 n ? 8 d3 n ? 8 d2 n ? 8 d1 n ? 8 d0 n ? 8 d10 n ? 7 msb n ? 7 n ? 1 n t data t frame t fco t pd t cpd t eh t a t el 0 6304-002 figure 2. 12-(preliminary) bit data serial stream (default) dco? dco+ dout? dout+ fco? fco+ ain clk? clk+ lsb (n ? 8) d0 (n ? 8) d1 (n ? 8) d2 (n ? 8) d3 (n ? 8) d4 (n ? 8) d5 (n ? 8) d6 (n ? 8) d7 (n ? 8) d8 (n ? 8) d9 (n ? 8) d10 (n ? 8) d0 (n ? 7) lsb (n ? 7) n ? 1 t a n t data t frame t fco t pd t cpd t eh t el 06304-004 figure 3. 12-(preliminary) bit data serial stream, lsb first
preliminary technical data AD9271 rev. pra | page 11 of 58 absolute maximum ratings table 4. parameter with respect to rating electrical avdd gnd ?0.3 v to +2.0 v drvdd gnd ?0.3 v to +2.0 v cwvdd gnd ?0.3 v to +3.9 v gnd gnd ?0.3 v to +0.3 v avdd drvdd ?2.0 v to +2.0 v digital outputs (dout+, dout?, dco+, dco?, fco+, fco?) gnd ?0.3 v to +2.0 v clk+, clk? gnd ?0.3 v to +3.9 v li-x lg-x ?0.3 v to +2.0 v lo-x lg-x ?0.3 v to +2.0 v losw-x lg-x ?0.3 v to +2.0 v cwdx?, cwdx+ gnd ?0.3 v to +2.0 v sdio, gain+,gain? gnd ?0.3 v to +2.0 v pdwn, stby, sclk, csb gnd ?0.3 v to +3.9 v reft, refb, rbias gnd ?0.3 v to +2.0 v vref, sense gnd ?0.3 v to +2.0 v environmental operating temperature range (ambient) ?40c to +85c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal impedance table 5. air flow velocity (m/s) ja 1 jb jc 0.0 20.3c/w 1.0 14.4c/w 7.6c/w 4.7c/w 2.5 12.9c/w 1 ja for a 4-layer pcb with solid ground plane (simulated). exposed pad soldered to pcb. esd caution
AD9271 preliminary technical data rev. pra | page 12 of 58 pin configuration and fu nction descriptions li-f lg-f lo-f li-g lg-g lo-g avdd clk? clk+ avdd avdd avdd avdd li-e lg-e avdd avdd li-h lg-h lo-h avdd avdd losw-f losw- g losw-h 06304-005 AD9271 top view (not to scale) exposed paddle, pin 0 (bottom of package) pin 1 indicator 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 avdd 74 75 pwdn 73 stby 72 drvdd 71 dout + a 70 dout ? a 69 dout + b 68 dout ? b 67 dout + c 66 dout ? c 65 dout + d 64 dout ? d 63 fco+ 62 fco? 61 dco+ 60 dco? 59 dout + e 58 dout ? e 57 dout + f 56 dout ? f 55 dout + g 54 dout ? g 53 dout + h 52 dout ? h 51 drvdd avdd li-a lg-a losw-a li-b lg-b lo-b avdd sdio sclk csb avdd avdd li-c lg-c lo-c avdd avdd li-d lg-d avdd avdd lo-a losw-b losw-c losw-d lo?d cwd0? cwd0+ cwd1? cwd1+ cwd2? cwd2+ cwvd-d gain? gain+ rbias sense vref refb reft avdd cwd3? cwd3+ cwd4? cwd4+ cwd5? cwd5+ lo?e losw-e figure 4. 100-lead tqfp table 6. pin function descriptions pin no. name description 0 gnd ground (exposed paddle should be tied to a quiet analog ground) 3, 4, 9, 10, 15, 16, 21, 22, 25, 50, 54, 55, 60, 61, 66, 67, 72, 73,92 avdd 1.8 v analog supply 26, 47 drvdd 1.8 v digital output driver supply 84 cwvdd 3.3 v analog supply 1 li-e lna analog input for channel e 2 lg-e lna ground for channel e 5 lo-f lna analog output for channel f 6 losw-f lna analog output complement for channel f 7 li-f lna analog input for channel f 8 lg-f lna ground for channel f 11 lo-g lna analog output for channel g 12 losw-g lna analog output complement for channel g 13 li-g lna analog input for channel g 14 lg-g lna ground for channel g
preliminary technical data AD9271 rev. pra | page 13 of 58 pin no. name description 17 lo-h lna analog output for channel h 18 losw-h lna analog output complement for channel h 19 li-h lna analog input for channel h 20 lg-h lna ground for channel h 23 clk? clock input complement 24 clk+ clock input true 27 dout ? h adc h digital output complement 28 dout + h adc h true digital output true 29 dout ? g adc c digital output complement 30 dout + g adc c true digital output 31 dout ? f adc b digital output complement 32 dout + f adc b true digital output true 33 dout ? e adc a digital output complement 34 dout + e adc a true digital output true 35 dco? frame clock digital output complement 36 dco+ frame clock digital output true 37 fco? frame clock digital output complement 38 fco+ frame clock digital output true 39 dout ? d adc h digital output complement 40 dout + d adc h true digital output true 41 dout ? c adc c digital output complement 42 dout + c adc c true digital output 43 dout ? b adc b digital output complement 44 dout + b adc b true digital output true 45 dout ? a adc a digital output complement 46 dout + a adc a true digital output true 48 stdby standby power down 49 pdwn full power down 51 sclk serial clock 52 sdio serial data input/output 53 csb chip select bar 56 lg-a lna ground for channel a 57 li-a lna analog input for channel a 58 losw-a lna analog output complement for channel a 59 lo-a lna analog output for channel a 62 lg-b lna ground for channel b 63 li-b lna analog input for channel b 64 losw-b lna analog output complement for channel b 65 lo-b lna analog output for channel b 68 lg-c lna ground for channel c 69 li-c lna analog input for channel c 70 losw-c lna analog output complement for channel c 71 lo-c lna analog output for channel c 74 lg-d lna ground for channel d 75 li-d lna analog input for channel d 76 losw-d lna analog output complement for channel d 77 lo-d lna analog output for channel d 78 cwd0? cw doppler output complement for channel 0 79 cwd0+ cw doppler output true for channel 0 80 cwd1? cw doppler output complement for channel 1 81 cwd1+ cw doppler output true for channel 1 82 cwd2? cw doppler output complement for channel 2 83 cwd2+ cw doppler output true for channel 2
AD9271 preliminary technical data rev. pra | page 14 of 58 pin no. name description 85 gain? gain control voltage input complement 86 gain+ gain control voltage input true 87 rbias external resistor sets th e internal adc core bias current 88 sense reference mode selection 89 vref voltage reference input/output 90 refb differential reference (negative) 91 reft differential reference (positive) 93 cwd3? cw doppler output complement for channel 3 93 cwd3+ cw doppler output true for channel 3 95 cwd4? cw doppler output complement for channel 4 96 cwd4+ cw doppler output true for channel 4 97 cwd5? cw doppler output complement for channel 5 98 cwd5+ cw doppler output true for channel 5 99 lo-e lna analog output for channel e 100 losw-e lna analog output complement for channel e
preliminary technical data AD9271 rev. pra | page 15 of 58 equivalent circuits li-x, lg-x avdd 15k ? v cm 06304-073 figure 5. equivalent lna input circuit lo-x, losw-x 10 ? 06304-075 avdd figure 6. equivalent lna output circuit 10 ? 10k ? 10k ? clk? 10 ? 1.25v clk+ 06304-007 figure 7. equivalent clock input circuit sdio 350 ? 30k ? 06304-008 a vdd figure 8. equivalent sdio input circuit dr v dd drgnd dout? dout+ v v v v 0 6304-009 figure 9. equivalent digital output circuit s clk or pdwn or stby 30k ? 1k ? 06304-010 figure 10. equivalent sclk input circuit
AD9271 preliminary technical data rev. pra | page 16 of 58 100 ? rbias 06304-011 avdd figure 11. equivale nt rbias circuit csb 70k ? 1k ? a v dd 06304 -012 figure 12. equivalent csb input circuit sense 1k ? 06304 -013 figure 13. equivalent sense circuit vref 6k ? 0 6304 -014 avdd figure 14. equivalent vref circuit gain 50 ? 06304-074 figure 15. equivalent gain input circuit c wdx+, cwdx? 10 ? 06304-076 figure 16. equivalent cwd output circuit
preliminary technical data AD9271 rev. pra | page 17 of 58 typical performance characteristics (f sample = 50 msps, ain = 5 mhz, lpf = 1/3 f sample , lna gain = 6) -2.00 -1.50 -1.00 -0.50 0.00 0.50 1.00 1.50 2.00 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 vgain (v) absolute error (db) 85c 25c -40c figure 17. absolute gain error vs. v gain at three temperatures figure 18. gain error histogram figure 19. gain match histogram for v gain = 0.2 v and 0.7 v 0 200000 400000 600000 800000 1000000 1200000 1400000 1600000 1800000 2000000 -5-4-3-2-1012345 codes number of hits figure 20. output-referred noise histog ram with gain pin at 0.0v, AD9271- 50 0 200000 400000 600000 800000 1000000 1200000 -5-4-3-2-1012345 codes number of hits figure 21. output-referred noise histog ram with gain pin at 1.0v, AD9271- 50 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 10 15 20 25 frequency (mhz) input-referred noise (nv/sqrt-hz) lna gain = 5x lna gain = 6x lna gain = 8x figure 22. short-circuit, inpu t-referred noise vs. frequency
AD9271 preliminary technical data rev. pra | page 18 of 58 -108 -107 -106 -105 -104 -103 -102 -101 -100 -99 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 vgain (v) output-referred noise (dbfs/rt-hz) lna gain = 5x lna gain = 6x lna gain = 8x figure 23. short-circuit, output-referred noise vs. v gain 52 54 56 58 60 62 64 66 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 vgain (v) snr/sinad snr (dbfs) sinad (db) sinad (dbfs) figure 24. snr/sinad vs. gain 1.4 1.45 1.5 1.55 1.6 1.65 1.7 -40-20 0 20406080 temperature (c) input-referred noise (nv/rt-hz) figure 25. short-circuit, input-referred noise vs. temperature -40 -35 -30 -25 -20 -15 -10 -5 0 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 frequency (mhz) fundamental (dbfs) (1/3)*50mhz (1/3)*40mhz (1/3)*25mhz -3db line figure 26. antialiasing filter (aaf) pass-band response 0 50 100 150 200 250 300 350 400 0.1 1 10 100 analog input frequency (mhz) group delay (n s) vgain = 0.0 v vgain = 0.5 v vgain = 1.0 v figure 27. antialiasing filter (aaf) group delay response -85 -80 -75 -70 -65 -60 -55 -50 2 4 6 8 10 12 14 16 fin (mhz) h2 (dbfs) vgain=0.2v vgain=0.5v vgain=1v figure 28. second-order harmonic distortion vs. frequency
preliminary technical data AD9271 rev. pra | page 19 of 58 -85 -80 -75 -70 -65 -60 -55 -50 2 4 6 8 10121416 fin (mhz) h3 (dbfs) vgain=0.2v vgain=0.5v vgain=1v figure 29. third-order harmonic distortion vs. frequency -110 -100 -90 -80 -70 -60 -50 -40 -40 -35 -30 -25 -20 -15 -10 -5 0 adc output level (dbfs) second harmonic (dbfs) vgain=0v vgain=0.5v vgain=1v figure 30. second-order harmonic distortion vs. adc output level -110 -100 -90 -80 -70 -60 -50 -40 -40 -35 -30 -25 -20 -15 -10 -5 0 adc output level (dbfs) third harmonic (dbfs) vgain=0v vgain=0.5v vgain=1v figure 31. third-order harmonic distortion vs. adc output level
AD9271 preliminary technical data rev. pra | page 20 of 58 theory of operation ultrasound the primary application for the AD9271 is medical ultrasound. figure 32 shows a simplified block diagram of an ultrasound system. a critical function of an ultrasound system is the time gain control (tgc) compensation for physiological signal attenuation. because the attenuation of ultrasound signals is exponential with respect to distance (time), a linear-in-db vga is the optimal solution. key requirements in an ultrasound signal chain are very low noise, active input termination, fast overload recovery, low power, and differential drive to an adc. because ultrasound machines use beam-forming techniques requiring large binary- weighted numbers (for example, 32 to 512) of channels, the lowest power at the lowest possible noise is of key importance. most modern machines use digital beam forming. in this technique, the signal is converted to digital format immediately following the tgc amplifier; beam forming is done digitally. the adc resolution of 12 bits with up to 50 msps sampling satisfies the requirements of both general-purpose and high- end systems. power consumption and low cost are of primary importance in low-end and portable ultrasound machines, and the AD9271 is designed for these criteria. for additional information regarding ultrasound systems, refer to how ultrasound system considerations influence front-end component choice , analog dialogue , volume 36, number 3, mayCjuly 2002. beamformer central control rx beamformer (b and f modes) color doppler (pw) processing (f mode) image and motion processing (b mode) spectral doppler processing mode display audio output tx beamformer cw (analog) beamformer transducer array 128, 256 etc. elements bidirectional cable hv mux/ demux t/r switches tx hv amps multichannel tgc uses many vgas tgc time gain compensation 06304-077 AD9271 aaf vga lna adc cw figure 32. simplified ultrasound system block diagram
preliminary technical data AD9271 rev. pra | page 21 of 58 lna li-x lg-x lo-x dout ? x dout + x cs clg cfb rfb2 csh gain interpolator rs serial port interface losw-x rfb1 to switch array g m cdw+ cdw? attenuator ?30db to 0db gain? csb sclk sdio 12-bit pipeline adc serial lvds +24db 06304-071 aaf gain+ AD9271 figure 33. simplified block diagram of single channel channel overview each channel contains both a tgc and cw doppler signal path. common to both signal paths, the lna provides user- adjustable input impedance termination. the cw doppler path includes a transconductance amplifier and crosspoint switch. the tgc path includes a differential x-amp? vga, an antialiasing filter, and an adc. figure 33 shows a simplified block diagram with external components. the signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the lna is designed to be driven from a single-ended signal source. low noise amplifier (lna) good noise performance relies on a proprietary ultralow noise lna at the beginning of the signal chain, which minimizes the noise contribution in the following vga. active impedance control optimizes noise performance for applications that benefit from input impedance matching. a simplified schematic of the lna is shown in figure 34. li-x is capacitively coupled to the source. an on-chip bias generator establishes dc input bias voltages of around 1.4 v and centers the output common-mode levels at 0.9 v (vdd/2). a capacitor, c lg , of the same value as the input coupling capacitor, c s , is connected from the lg-x pin to ground. li-x cs clg cfb csh rs lg-x lo-x losw rfb1 rfb2 06304-101 figure 34. simplifi ed lna schematic the lna supports differential output voltages as high as 2 v p-p with positive and negative excursions of 0.5 v from a common-mode voltage of 0.9 v. the lna differential gain sets the maximum input signal before saturation. one of three gains is set through the spi. the corresponding input full-scale for the gain settings of 5, 6, or 8 is 400 mv p-p, 333 mv p-p, and 250 mv p-p, respectively. overload protection ensures quick recovery time from large input voltages. because the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the esd protection. low value feedback resistors and the current-driving capability of the output stage allow the lna to achieve a low input-referred noise voltage of 1.2 nv/hz. this is achieved with a current consumption of only 16 ma per channel (30 mw). on-chip resistor matching results in precise single-ended gains critical for accurate impedance control. the use of a fully differential topology and negative feedback minimizes distortion. low hd2 is particularly important in second harmonic ultrasound imaging applications. differential signaling enables smaller swings at each output, further reducing third-order distortion. active impedance matching the lna consists of a single-ended voltage gain amplifier with differential outputs and the negative output externally available. for example, with a fixed gain of 6 (15.6 db), an active input termination is synthesized by connecting a feedback resistor between the negative output pin, lo-x, and the positive input pin, li-x. this technique is well known and results in the input resistance shown in equation 2, where a/2 is the single-ended gain or the gain from the li-x inputs to the lo-x outputs. ) 2 1 ( a r r fb in + = (2)
AD9271 preliminary technical data rev. pra | page 22 of 58 because the amplifier has a gain of 6 from its input to its differential output, it is important to note that the gain a/2 is the gain from pin li-x to pin lo-x, and is 6 db less than the gain of the amplifier, or 9.6 db (3). the input resistance is reduced by an internal bias resistor of 15 k in parallel with the source resistance connected to pin li-x, with pin lg-x ac grounded. equation 3 can be used to calculate the needed r fb for a desired r in , even for higher values of r in . + = k 15 || ) 3 1 ( fb in r r (3) for example, to set r in to 200 , the value of r fb is 845 . if the simplified equation, equation 2, is used to calculate r in , the resulting value is 190 , resulting in a less than 0.1 db gain error. factors such as a dynamic source resistance might influence the absolute gain accuracy more significantly. at higher frequencies, the input capacitance of the lna needs to be considered. the user must determine the level of matching accuracy and adjust r fb accordingly. the bandwidth (bw) of the lna is about 70 mhz. ultimately the bw of the lna limits the accuracy of the synthesized r in . for r in = r s up to about 200 , the best match is between 100 khz and 10 mhz, where the lower frequency limit is determined by the size of the ac-coupling capacitors, and the upper limit, by the lna bw. furthermore, the input capacitance and r s limit the bw at higher frequencies. frequency (hz) input impedance ( ) 100 1k 10 1m 100k 50m 10m r in = 50 , r fb = 249 r sh = , c sh = 0 pf r sh = 50 , c sh = 22 pf r in = 100 , r fb = 499 r in = 200 , r fb = 1k r sh = , c sh = 0 pf r sh = 50 , c sh = 22 pf r in = 500 , r fb = 2.5k figure 35. r in vs. frequency for various values of r fb (effects of r sh and c sh are also shown figure 35 shows r in vs. frequency for various values of r fb . note that at the lowest value, 50 , r in peaks at frequencies greater than 10 mhz. this is due to the bw roll-off of the lna as mentioned earlier. however, as can be seen for larger r in values, parasitic capacitance starts rolling off the signal bw before the lna can produce peaking. c sh further degrades the match; therefore, c sh should not be used for values of r in that are greater than 100 . table 7 lists the recommended values for r fb and c sh in terms of r in . c fb is needed in series with r fb because the dc levels at pin lo-x and pin li-x are unequal. table 7. active termination external component values lna gain r in () r fb () minimum c sh (pf) bw (mhz) 5 50 175 90 49 6 50 200 70 59 8 50 250 50 73 5 100 350 30 49 6 100 400 20 59 8 100 500 10 73 5 200 700 na 49 6 200 800 na 49 8 200 1000 na 49 lna noise the short-circuit noise voltage (input-referred noise) is an important limit on system performance. the short-circuit noise voltage for the lna is 1.2 nv/hz or 1.4 nv/hz (at maximum gain), including the vga noise. these measurements, which are taken without a feedback resistor, provide the basis for calculating the input noise and noise figure performance of the configurations shown in figure 43. figure 43 and figure 44 are simulations of noise figure vs. r s results using these configurations and an input-referred noise voltage for the vga of 4 nv/hz. unterminated (r fb = ) operation exhibits the lowest equivalent input noise and noise figure. figure 44 shows the noise figure vs. source resistance rising at low r s where the lna voltage noise is large compared with the source noise and at high r s due to current noise. v out unterminated + ? v in r in r s v out resistive termination + ? v in r in r s r s v out active impedance match + ? v in r in r fb r fb 1 + a/2 r s r in = 03199-079 figure 36. input configurations
preliminary technical data AD9271 rev. pra | page 23 of 58 7 6 5 4 3 2 1 0 50 100 1k noise figure (db) r s ( ? ) 03199-076 includes noise of vga resistive termination (r s = r in ) active impedance match unterminated simulation figure 37. noise figure vs. r s for resistive, active matched and unterminated inputs, gain = 1 v 7 6 5 4 3 2 1 0 50 100 1k noise figure (db) r s ( ? ) 03199-077 includes noise of vga r in = 50 ? r in = 75 ? r in = 100 ? r in = 200 ? r fb = simulation figure 38. noise figure vs. r s for various fixed values of r in , actively matched, gain = 1 v . the primary purpose of input impedance matching is to improve the system transient response. with resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the lnas input voltage noise generator. with active impedance matching, however, the contributions of both are smaller than they would be for resistive termination by a factor of 1/(1 + lna gain ). figure 37 shows the relative noise figure (nf) performance. in this graph, the input impedance was swept with r s to preserve the match at each point. the noise figures for a source impedance of 50 are 7.1 db, 4.1 db, and 2.5 db for the resistive, active, and unterminated configurations, respectively. the noise figures for 200 are 4.6 db, 2.0 db, and 1.0 db, respectively. figure 38 shows the nf vs. r s for various values of r in , which is helpful for design purposes. the plateau in the nf for actively matched inputs mitigates source impedance variations. for comparison purposes, a preamp with a gain of 15.6 db and noise spectral density of 1.2 nv/hz, combined with a vga with 4 nv/hz, yields a noise figure degradation of approximately 1.5 db (for most input impedances), which is significantly worse than the AD9271 performance. input overdrive excellent overload behavior is of primary importance in ultra- sound. both the lna and vga have built-in overdrive protection and quickly recover after an overload event. input overload protection as with any amplifier, voltage clamping prior to the inputs is highly recommended if the application is subject to high transient voltages. a block diagram of a simplified ultrasound transducer interface is shown in figure 39. a common transducer element serves the dual functions of transmitting and receiving ultrasound energy. during the transmitting phase, high voltage pulses are applied to the ceramic elements. a typical transmit/receive (t/r) switch may consist of four high voltage diodes in a bridge configuration. although the diodes ideally block transmit pulses from the sensitive receiver input, diode characteristics are not ideal, and resulting leakage transients imposed on the li-x inputs can be problematic. because ultrasound is a pulse system and time-of-flight is used to determine depth, quick recovery from input overloads is essential. overload can occur in the preamp and the vga. immediately following a transmit pulse, the typical vga gains are low, and the lna is subject to overload from t/r switch leakage. with increasing gain, the vga can become overloaded due to strong echoes that occur near field echoes and acoustically dense materials, such as bone. figure 39 illustrates an external overload protection scheme. a pair of back-to-back schottky diodes is installed prior to installing the ac-coupling capacitors. although the bas40 diodes are shown, any diode is prone to exhibiting some amount of shot noise. many types of diodes are available for achieving the desired noise performance. the configuration shown in figure 39 tends to add 2 nvhz of input-referred noise. decreasing the 5 k resistor and increasing the 2 k resistor may improve noise contribution, depending on the application. with the diodes shown in figure 39, clamping levels of 0.5 v or less significantly enhances the system overload performance. 0 6304-100 transducer 10nf 10nf 2k ? 5k ? 5k ? AD9271 tx driver hv bas40-04 +5 v ?5v lna figure 39. input overload protection cw doppler operation modern ultrasound machines used for medical applications employ a 2 n binary array of receivers for beam forming, with
AD9271 preliminary technical data rev. pra | page 24 of 58 typical array sizes of 16 or 32 receiver channels phase-shifted and summed together to extract coherent information. when used in multiples, the desired signals from each of the channels can be summed to yield a larger signal (increased by a factor n, where n is the number of channels), and the noise is increased by the square root of the number of channels. this technique enhances the signal-to-noise performance of the machine. the critical elements in a beam-former design are the means to align the incoming signals in the time domain and the means to sum the individual signals into a composite whole. beam forming, as applied to medical ultrasound, is defined as the phase alignment and summation of signals that are generated from a common source but received at different times by a multielement ultrasound transducer. beam forming has two functions: it imparts directivity to the transducer, enhancing its gain, and it defines a focal point within the body from which the location of the returning echo is derived. the AD9271 includes the front-end components needed to implement analog beam forming for cw doppler operation. these components allow cw channels with similar phases to be coherently combined before phase alignment and down mixing, thus reducing the number of delay lines or adjustable phase shifters/down mixers (ad8333 or ad8339) required. next, if delay lines are used, the phase alignment is performed and then the channels are coherently summed and down converted by a dynamic range i/q demodulator. alternatively, if phase shifters/ down mixers, such as the ad8333 and ad8339, are used, phase alignment and down conversion are done before coherently summing all channels into i/q signals. in either case, the resultant i and q signals are filtered and sampled by two high resolution adcs, and the sampled signals are processed to extract the relevant doppler information. AD9271 lna g m g m g m g m g m g m g m g m switch array 8 AD9271 8 channel 16-bit adc opa q i lna lna lna AD9271 lna switch array 8 channel lna lna lna 3 ad8333 2.5v ad8333 2.5v 2.5v 2.5v ad8333 16-bit adc opa 06304-096 600nh 600nh 600nh 600nh 600nh 700 ? 700 ? 700 ? 700 ? 600nh 600nh 600nh figure 40. typical cw doppler system using the AD9271 and ad8339
preliminary technical data AD9271 rev. pra | page 25 of 58 crosspoint switch each lna is followed by a transconductance amp for v/i con- version. currents can be routed to one of six pairs of differential outputs or to 12 single-ended outputs for summing. each cwd output pin sinks 2.4 ma dc current, and the signal has a full-scale of 2 ma for each channel selected by the cross-point switch. for example, if four channels were to be summed on one cwd output, the output would sink 9.6 ma dc and have a full-scale current output of 8 ma. the maximum number of channels combined must be considered in setting the load impedance for i/v conversion to ensure that the full-scale swing and common- mode voltage are within the operating limits of the AD9271. when interfacing to the ad8339, a common-mode voltage of 2.5 v and a full-scale swing of 2.8 v p-p are desired this can be accomplished by connecting an inductor between each cwd output and a 2.5 v supply, and then connecting either a single- ended or differential load resistance to the cwd outputs. the value of resistance should be calculated based on the maximum number of channels that can be combined. cwd outputs are required under full-scale swing to be within 1.5 v and cwvdd (3.3 v supply). tgc operation the signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the lnas are designed to be driven from a single-ended signal source. gain values are referenced from the single-ended lna input to the differential output of the lna. a simple exercise in understanding the maximum and minimum gain requirements is shown in figure 41. table 8. lna specifications lna parameters specifications bw (mhz) 15 fs/fsrms (mvpp/mv) 333/118 snr (db) 88.1 enob (bits) 14.3 noise (rms uv/nv/rt(hz)) 4.65/1.2 a dc equivalent a dc equivalent dynamic range lna fs (0.333v p-p se) vga noise floor (4.7v rms) adc fs (2v p-p) adc noise floor (194v rms) minimum gain maximum gain 06304-097 88db 70db figure 41. gain requirements of tgc for a 12-bit, 40 msps adc table 9. adc specifications adc parameters specifications fs/fsrms (vpp/mv) 2/707 snr (db) 70 enob (bits) 11.3 sfdr (db) ?82 noise (rms uv/nv/rt(hz)) 194/50 in summary, the maximum gain required is determined by ( adc noise floor / vga input noise floor ) + margin = 20 log(194/4.7) + 10 db = 42.3 db the minimum gain required is determined by ( adc input fs / vga input fs ) + margin = 20 log(2/0.333) C 6 db = 9.6 db therefore, a 12-bit, 40 msps adc with 15 mhz of bandwidth should suffice in achieving the dynamic range required for most ultrasound systems today. the system gain is distributed as listed in table 7. table 10. channel gain distribution section nominal gain (db) lna 14/15.6/18 attenuator 0 to ?30 vga amp 25 filter 0 adc 0 total 9 to 39/10.6 to 40.6/13 to 43 the linear-in-db gain range of the tgc path is 30 db, extending from 9.6 db to 39.6 db. the slope of the gain control interface is 30 db/v, and the gain control range is 0 v to 1 v. equation 1 is the expression for gain. icpt v db gain gain + = v db 30 ) ( (1) where icpt is the intercept point of the lna gain. in its default condition, the lna has a gain of 15.6 db (6) and the vga gain is ?6 db if the voltage on the v gain pin is 0 v. this gives rise to a total gain (or icpt) of 9.6 db through the tgc path if the lna input is unmatched, or of 3.6 db if the lna is matched to 50 (r fb = 200 ). if the voltage on the v gain pin is 1 v, however, the vga gain is 24 db. this gives rise to a total gain of 39.6 db through the tgc path if the lna input is unmatched, or of 33.5 db if the lna input is matched. each of the lna outputs is dc-coupled to a vga input. the vga consists of an attenuator with a range of 30 db followed by an amplifier with 24 db of gain for a net gain range of ?5 db to +25 db. the x-amp gain-interpolation technique results in low
AD9271 preliminary technical data rev. pra | page 26 of 58 gain error and uniform bandwidth, and differential signal paths minimize distortion. at low gain the vga should limit the system noise performance (snr), whereas at high gains the noise is defined by the source and lna. the maximum voltage swing is bounded by the full- scale peak-to-peak adc input voltage (2 v p-p). variable gain amplifier the differential x-amp vga provides precise input attenuation and interpolation. it has a low input-referred noise of 4 nv/hz and excellent gain linearity. a simplified block diagram is shown in figure 42. 06304-078 vip gain 3db vin g m postamp postamp + ? gain interpolator figure 42. simplifi ed vga schematic the input of the vga is a 12-stage differential resistor ladder with 3.01 db per tap. the resulting total gain range is 30 db, which allows for range loss at the endpoints. the effective input resistance per side is 180 nominally for a total differential resistance of 360 . the ladder is driven by a fully differential input signal from the lna. lna outputs are dc-coupled to avoid external decoupling capacitors. the common-mode voltage of the attenuator and the vga is controlled by an amplifier that uses the same midsupply voltage derived in the lna, permitting dc coupling of the lna to the vga without introducing large offsets due to common- mode differences. however, any offset from the lna will be amplified as the gain is increased, producing an exponentially increasing vga output offset. the input stages of the x-amp are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. with overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from 0 db to ?30 db. this circuit technique results in linear-in-db gain law conformance and low distortion levelsonly deviating 0.2 db or less from the ideal. the gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. the x-amp inputs are part of a 25 db gain feedback amplifier that completes the vga. its bandwidth is about 80 mhz. the input stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity across the gain setting. gain control the gain control interface, gain+, is a differential input. v gain varies the gain of all vgas through the interpolator by selecting the appropriate input stages connected to the input attenuator. the nominal v gain range for 30 db/v is 0 v to 1 v, with the best gain-linearity from about 0.1 v to 0.9 v, where the error is typically less than 0.2 db. for v gain voltages greater than 0.9 v and less than 0.1 v, the error increases. the value of the v gain voltage can be increased to that of the supply voltage without gain foldover. gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain. there are two ways in which the gain pins can be interfaced. using a single-ended method, a kelvin type of connection to ground should be used as shown in figure 43. for driving multiple devices, it is preferred to use a differential method as shown in figure 44. in either method, the gain pins should be dc-coupled and driven to accommodate a 1 v full-scale input. figure 43. single-ended gain pin configuration gain? 50 ? gain+ AD9271 avdd 26k ? 10k ? 0.01f 0.25dc at 0.5v cm 0.25dc at 0.5v cm 100 ? 499 ? 0.5v dc 0.01f 100 ? 499 ? 523 ? 499 ? 0.5v cm ad8318 0 6304-098 figure 44. differential gain pin configuration vga noise in a typical application, a vga compresses a wide dynamic range input signal to within the input span of an adc. the input-referred noise of the lna limits the minimum resolvable input signal, whereas the output-referred noise, which depends primarily on the vga, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. this limit is set in accordance with the quantization noise floor of the adc. output- and input-referred noise as a function of v gain are shown in figure tbd and figure tbd for the short-circuited input conditions. the input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. the output-referred noise is a flat 65 nv/hz over most of the gain range, because it is dominated by the fixed output-referred noise of the vga. at the high end of the gain control range, the
preliminary technical data AD9271 rev. pra | page 27 of 58 noise of the lna and source prevail. the input-referred noise reaches its minimum value near the maximum gain control voltage, where the input-referred contribution of the vga is miniscule. at lower gains, the input-referred noise, and therefore the noise figure, increases as the gain decreases. the instantaneous dynamic range of the system is not lost, however, because the input capacity increases as the input-referred noise increases. the contribution of the adc noise floor has the same dependence. the important relationship is the magnitude of the vga output noise floor relative to that of the adc. gain control noise is a concern in very low noise applications. thermal noise in the gain control interface can modulate the channel gain. the resultant noise is proportional to the output signal level and usually only evident when a large signal is present. the gain interface includes an on-chip noise filter, which reduces this effect significantly at frequencies above 5 mhz. care should be taken to minimize noise impinging at the gain input. an external rc filter can be used to remove v gain source noise. the filter band- width should be sufficient to accommodate the desired control bandwidth. antialiasing filter the filter that the signal reaches prior to the adc is used to reject dc signals and to bandlimit the signal for antialiasing. figure 45 shows the architecture of the filter. 2k ? 2k ? 2k ? 2k ? 2k ? 2k ? *c = 0.5 to 3.1pf 6.5c* 7.5c* 1c* 1c* 4k ? 4k ? 56/112pf 56/112pf 06304-099 figure 45. simplified filter schematic the filter can be configured for dc coupling or to have a single pole for high-pass filtering at either 700 khz or 350 khz (programmed through the spi). the high-pass pole, however, is not tuned and can vary by 30%. a third-order butterworth low-pass filter is used to reduce noise bandwidth and provide antialiasing for the adc. the filter uses on-chip tuning to trim the capacitors to set the desired cutoff and reduce variation. the default ?3db cutoff is 1/3 the adc sample clock rate. the cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the spi. the cutoff can be set from 8 mhz to 18 mhz. tuning is normally off to avoid changing the capacitor settings during critical times. the tuning circuit is enabled and disabled through the spi. tuning should be done after initial power-up and after reprogramming the filter cutoff scaling or adc sample rate. occasional retuning during an idle time is recommended.
AD9271 preliminary technical data rev. pra | page 28 of 58 a/d converter the AD9271 architecture consists of a pipelined adc that is divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a 3-bit flash. each stage provides sufficient overlap to correct for flash errors in the preceding stages. the quantized outputs from each stage are combined into a 12-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on preceding samples. sampling occurs on the rising edge of the clock. each stage except for the last of the pipeline consists of a low resolution flash adc connected to a switched-capacitor dac and interstage residue amplifier (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage consists of a flash adc. the output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. the data is then serialized and aligned to the frame and output clock. clock input considerations for optimum performance, the AD9271 sample clock inputs (clk+ and clk?) should be clocked with a differential signal. this signal is typically ac-coupled into the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally and require no additional bias. figure 46 shows the preferred method for clocking the AD9271. the low jitter clock source, such as the valpey fisher oscillator vfac3-bhl-50mhz, is converted from single-ended to differential using an rf transformer. the back-to-back schottky diodes across the secondary transformer limit clock excursions into the AD9271 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9271 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsm2812 3.3v 50 ? 100 ? clk? clk+ adc AD9271 mini-circuits adt1?1wt, 1:1z xfmr 06304-050 vfac3 out en figure 46. transformer-coupled differential clock if a low jitter clock is available, another option is to ac-couple a differential pecl signal to the sample clock input pins as shown in figure 47. the ad951x family of clock drivers offers excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? ad951x family 50 ? * clk clk * 50 ? resistor is optional. clk? clk+ adc AD9271 06304-051 pecl driver 3.3v out vfac3 en figure 47. differential pecl sample clock 100 ? 0.1f 0.1f 0.1f 0.1f 50 ? * lvds driver clk clk * 50 ? resistor is optional. clk? clk+ adc AD9271 06304-052 ad951x family 3.3v out vfac3 en figure 48. differential lvds sample clock in some applications, it is acceptable to drive the sample clock inputs with a single-ended cmos signal. in such applications, clk+ should be driven directly from a cmos gate, and the clk? pin should be bypassed to ground with a 0.1 f capacitor in parallel with a 39 k resistor (see figure 48). although the clk+ input circuit supply is avdd (1.8 v), this input is designed to withstand input voltages up to 3.3 v, making the selection of the drive logic voltage very flexible. 0.1f 0.1f 0.1f 39k ? cmos driver 50 ? * optional 100 ? 0.1f clk clk * 50 ? resistor is optional. clk? clk+ adc AD9271 06304-053 ad951x family 3.3 v out vfac3 en figure 49. single-ended 1.8 v cmos sample clock 0.1f 0.1f 0.1f cmos driver 50 ? * optional 100 ? clk clk * 50 ? resistor is optional. 0.1f clk? clk+ adc AD9271 06304-054 ad951x family 3.3 v out vfac3 en figure 50. single-ended 3.3 v cmos sample clock clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sensitive to the clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the AD9271 contains a duty cycle
preliminary technical data AD9271 rev. pra | page 29 of 58 stabilizer (dcs) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the AD9271. when the dcs is on, noise and distortion performance are nearly flat for a wide range of duty cycles. however, some applications may require the dcs function to be off. if so, keep in mind that the dynamic range performance can be affected when operated in this mode. see the memory map section for more details on using this feature. the duty cycle stabilizer uses a delay-locked loop (dll) to create the nonsampling edge. as a result, any changes to the sampling frequency require approximately eight clock cycles to allow the dll to acquire and lock to the new rate. clock jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f a ) due only to aperture jitter (t j ) can be calculated by snr degradation = 20 log 10[1/2 f a t j ] in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter. if undersampling applications are particularly sensitive to jitter (see figure 51). the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9271. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources, such as the valpey fisher vfac3 series. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. refer to the an-501 application note and the an-756 application note for more in-depth information about jitter performance as it relates to adcs (visit www.analog.com ). 1 10 100 1000 16 bits 14 bits 12 bits 30 40 50 60 70 80 90 100 110 120 130 0.125ps 0.5ps 1.0ps 2.0ps analog input frequency (mhz) 10 bits 8 bits rms clock jitter requirement snr (db) 06304 -038 0.25ps figure 51. ideal snr vs. input frequency and jitter
AD9271 preliminary technical data rev. pra | page 30 of 58 power dissipation and power-down mode as shown in figure 52, the power dissipated by the AD9271 is proportional to its sample rate. the digital power dissipation does not vary much because it is determined primarily by the drvdd supply and bias current of the lvds output drivers. 0 100 200 300 400 500 600 700 800 0 102030405060 sampling frequency (msps) currents (ma) 25msps speed grade 40msps speed grade 50msps speed grade idrvdd figure 52. supply current vs. f sample for f in = 7.5 mhz 100 110 120 130 140 150 160 170 180 190 0 102030405060 sampling frequency (msps) power/channel (mw) 25msps speed grade 40msps speed grade 50msps speed grade figure 53. power per channel vs. f sample for f in = 7.5 mhz by asserting the pdwn pin high, the AD9271 is placed in power-down mode. in this state, the adc typically dissipates xx mw. during power-down, the lvds output drivers are placed in a high impedance state. the AD9271 returns to normal operating mode when the pdwn pin is pulled low. this pin is both 1.8 v and 3.3 v tolerant. by asserting the stby pin high, the AD9271 is placed in a standby mode. in this state, the adc typically dissipates xx mw. during standby, the entire part is powered down except the internal references. the lvds output drivers are placed in a high impedance state. this mode is well suited for applications that require power savings because it allows the device to be powered down when not in use and then quickly powered up. the time to power this device back up is also greatly reduced. the AD9271 returns to normal operating mode when the stby pin is pulled low. this pin is both 1.8 v and 3.3 v tolerant. in power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, pll, and biasing networks. the decoupling capacitors on reft and refb are discharged when entering power-down mode and must be recharged when returning to normal operation. as a result, the wake-up time is related to the time spent in the power-down mode; shorter cycles result in proportionally shorter wake-up times. with the recommended 0.1 f and 4.7 f decoupling capacitors on reft and refb, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and xx s to restore full operation. there are a number of other power-down options available when using the spi port interface. the user can individually power down each channel or put the entire device into standby mode. this allows the user to keep the internal pll powered up when fast wake-up times (~xxx ns) are required. see the memory map section for more details on using these features. digital outputs and timing the AD9271 differential outputs conform to the ansi-644 lvds standard on default power-up. this can be changed to a low power, reduced signal option similar to the ieee 1596.3 standard using the sdio/odm pin or via the spi. this lvds standard can further reduce the overall power dissipation of the device by approximately xx mw. see the sdio pin section or table 16 in the memory map section for more information. the lvds driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 ma. a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing at the receiver. the AD9271 lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas that have lvds capability for superior switching performance in noisy environments. single point-to-point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. no far-end receiver termination and poor differential trace routing may result in timing errors. it is recommended that the trace length is no longer than 24 inches and that the differential output traces are kept close together and at equal lengths. an example of the fco and data stream with proper trace length and position can be found in figure 54.
preliminary technical data AD9271 rev. pra | page 31 of 58 figure 54. lvds output timing example in ansi mode (default) an example of the lvds output using the ansi standard (default) data eye and a time interval error (tie) jitter histogram with trace lengths of less than 24 inches on regular fr-4 material is shown in figure 55. figure 56 shows an example of when the trace lengths exceed 24 inches on regular fr-4 material. notice that the tie jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position; therefore, the user must determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. additional spi options allow the user to further increase the internal termination (and therefore increase the current) of all eight outputs in order to drive longer trace lengths (see figure 57). even though this produces sharper rise and fall times on the data edges, is less prone to bit errors, and improves frequency distribution (see figure 57), the power dissipation of the drvdd supply increases when this option is used. in cases that require increased driver strength to the dco and fco outputs because of load mismatch register 15 allows the user to double the drive strength. to do this, set the appropriate bit in register 5. note that this feature cannot be used with bit 4 and bit 5 in register 15 because these bits take precedence over this feature. see the memory map section for more details. figure 55. data eye for lvds outputs in ansi mode with trace lengths of less than 24 inches on standard fr-4 figure 56. data eye for lvds outputs in ansi mode with trace lengths of greater than 24 inches on standard fr-4 figure 57. data eye for lvds outputs in ansi mode with 100 termination on and trace lengths of greater than 24 inches on standard fr-4 the format of the output data is offset binary by default. an example of the output coding format can be found in table 11. if it is desired to change the output data format to twos complement, see the memory map section. table 11. digital output coding code (vin+) ? (vin?), input span = 2 v p-p (v) digital output offset binary (d11 ... d0) 4095 +1.00 1111 1111 1111 2048 0.00 1000 0000 0000 2047 ?0.000488 0111 1111 1111 0 ?1.00 0000 0000 0000 data from each adc is serialized and provided on a separate channel. the data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 600 mbps (12 bits 50 msps = 600 mbps). the lowest typical conversion rate is 10 msps. however, if lower sample rates are required for a specific application, the pll can be set up for encode rates lower than 10 msps via the spi. this allows encode rates as low as 5 msps. see the memory map section for details on enabling this feature.
AD9271 preliminary technical data rev. pra | page 32 of 58 two output clocks are provided to assist in capturing data from the AD9271. the dco is used to clock the output data and is equal to six times the sampling clock (clk) rate. data is clocked out of the AD9271 and must be captured on the rising and falling edges of the dco that supports double data rate (ddr) capturing. the frame clock out (fco) is used to signal the start of a new output byte and is equal to the sampling clock rate. see the timing diagram shown in figure 2 for more information. table 12. flex output test modes output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data format select 0000 off (default) n/a n/a n/a 0001 midscale short 1000 0000 (8 bits) 10 0000 0000 (10 bits) 1000 0000 0000 (12 bits) 10 0000 0000 0000 (14 bits) same yes 0010 +full-scale short 1111 1111 (8 bits) 11 1111 1111 (10 bits) 1111 1111 1111 (12 bits) 11 1111 1111 1111 (14 bits) same yes 0011 ?full-scale short 0000 0000 (8 bits) 00 0000 0000 (10 bits) 0000 0000 0000 (12 bits) 00 0000 0000 0000 (14 bits) same yes 0100 checkerboard 1010 1010 (8 bits) 10 1010 1010 (10 bits) 1010 1010 1010 (12 bits) 10 1010 1010 1010 (14 bits) 0101 0101 (8 bits) 01 0101 0101 (10 bits) 0101 0101 0101 (12 bits) 01 0101 0101 0101 (14 bits) no 0101 pn sequence long 1 n/a n/a yes 0110 pn sequence short 1 n/a n/a yes 0111 one/zero word toggle 1111 1111 (8 bits) 11 1111 1111 (10 bits) 1111 1111 1111 (12 bits) 11 1111 1111 1111 (14 bits) 0000 0000 (8 bits) 00 0000 0000 (10 bits) 0000 0000 0000 (12 bits) 00 0000 0000 0000 (14 bits) no 1000 user input register 0x19 to register 0x 1a register 0x1b to register 0x1c no 1001 one/zero bit toggle 1010 1010 (8 bits) 10 1010 1010 (10 bits) 1010 1010 1010 (12 bits) 10 1010 1010 1010 (14 bits) n/a no 1010 1 sync 0000 1111 (8 bits) 00 0001 1111 (10 bits) 0000 0011 1111 (12 bits) 00 0000 0111 1111 (14 bits) n/a no 1011 one bit high 1000 0000 (8 bits) 10 0000 0000 (10 bits) 1000 0000 0000 (12 bits) 10 0000 0000 0000 (14 bits) n/a no 1100 mixed frequency 1010 0011 (8 bits) 10 0110 0011 (10 bits) 1010 0011 0011 (12 bits) 10 1000 0110 0111 (14 bits) n/a no 1 all test mode options, except pn sequence short and pn sequence long, can support 8- to 14-bit word lengths in order to verify data capture to the receiver.
preliminary technical data AD9271 rev. pra | page 33 of 58 when using the serial port interface (spi), the dco phase can be adjusted in 60 increments relative to the data edge. this enables the user to refine system timing margins if required. the default dco timing, as shown in figure 2, is 90 relative to the output data edge. an 8-, 10-, and 14-bit serial stream can also be initiated from the spi. this allows the user to implement different serial streams and test the devices compatibility with lower and higher resolution systems. when changing the resolution to an 8- or 10-bit serial stream, the data stream is shortened. when using the 14-bit option, the data stream stuffs two 0s at the end of the normal 14-bit serial data. when using the spi, all of the da ta outputs can also be inverted from their nominal state. this is not to be confused with inverting the serial stream to an lsb-first mode. in default mode, as shown in figure 2, the msb is represented first in the data output serial stream. however, this can be inverted so that the lsb is represented first in the data output serial stream (see figure 3). there are 12 digital output test pattern options available that can be initiated through the spi. this is a useful feature when validating receiver capture and timing. refer to table 12 for the output bit sequencing options available. some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. it should be noted that some patterns may not adhere to the data format select option. in addition, customer user patterns can be assigned in the 0x19, 0x1a, 0x1b, and 0x1c register addresses. all test mode options, except pn sequence short and pn sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. the pn sequence short pattern produces a pseudorandom bit sequence that repeats itself every 2 9 C 1 or 511 bits. a description of the pn sequence and how it is generated can be found in section 5.1 of the itu-t 0.150 (05/96) standard. for the AD9271, the only discrepancy from the itu standard is that the starting value is a specific value instead of all ones. see table 10 for initial values. the pn sequence long pattern produces a pseudorandom bit sequence that repeats itself every 2 23 C 1 or 8,388,607 bits. a description of the pn sequence and how it is generated can be found in section 5.6 of the itu-t 0.150 (05/96) standard. the only two discrepancies between the itu standard and the AD9271 pn sequence long implementation are as follows. first, the starting value is a specific value instead of all ones. second, the AD9271 inverts the bit stream with relation to the itu standard. see table 10 for initial values. table 10. pn sequence initial value first 3 output samples (msb 1st) pn sequence short 0x0df 0xdf9, 0x353, 0x301 pn sequence long 0x29b80a 0x591, 0xfd7, 0a3 consult the memory map section for information on how to change these additional digital output timing features through the serial port interface or spi. sdio pin this pin is required to operate the spi port interface. it has an internal 30 k pull-down resistor that pulls this pin low and is only 1.8 v tolerant. if applications require that this pin be driven from a 3.3 v logic level, insert a 1 k resistor in series with this pin to limit the current. sclk pin this pin is required to operate the spi port interface. it has an internal 30 k pull-down resistor that pulls this pin low and is both 1.8 v and 3.3 v tolerant. csb pin this pin is required to operate the spi port interface. it has an internal 70 k pull-down resistor that pulls this pin low and is both 1.8 v and 3.3 v tolerant. rbias pin to set the internal core bias current of the adc, place a resistor (nominally equal to 10.0 k) to ground at the rbias pin. the resistor current is derived on-chip and sets the adcs avdd current to a nominal xxx ma at 50 msps. therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. voltage reference a stable and accurate 0.5 v voltage reference is built into the AD9271. this is gained up internally by a factor of 2, setting v ref to 1.0 v, which results in a full-scale differential input span of 2 v p-p for the adc. the v ref is set internally by default; however, the vref pin can be driven externally with a 1.0 v reference to achieve more accuracy. when applying the decoupling capacitors to the vref, reft, and refb pins, use ceramic low esr capacitors. these capacitors should be close to reference pins and on the same layer of the pcb as the AD9271. the recommended capacitor values and configurations for the AD9271 reference pin can be found in figure 58.
AD9271 preliminary technical data rev. pra | page 34 of 58 table 13. reference settings selected mode sense voltage resulting vref (v) resulting differential span (v p-p) external reference avdd n/a 2 external reference internal, 2 v p-p fsr agnd to 0.2 v 1.0 2.0 internal reference operation a comparator within the AD9271 detects the potential at the sense pin and configures the reference. if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 58), setting vref to 1 v. the reft and refb pins establish their input span of the adc core from the reference configuration. the analog input full- scale range of the adc equals twice the voltage at the reference pin for either an internal or an external reference configuration. 1f 0.1f v ref sense 0.5v reft 0.1f 0.1f 4.7f 0.1f refb select logic adc core + vin? vin+ 06304-064 figure 58. internal reference configuration 1f* 0.1f* v ref sense avdd 0.5v reft 0.1f 0.1f 4.7f 0.1f refb select logic adc core + vin? vin+ external reference *optional. 0 6304-065 figure 59. external reference operation external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift charac- teristics. figure 61 shows the typical drift characteristics of the internal reference in 1 v mode. when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. the external reference is loaded with an equivalent 6 k load. an internal reference buffer generates the positive and negative full-scale references, reft and refb, for the adc core. therefore, the external reference must be limited to a nominal of 1.0 v. -25 -20 -15 -10 -5 0 5 00.511.522.533.5 current load (ma) vref error (%) figure 60. v ref accuracy vs. load, AD9271-50 -0.2 -0.18 -0.16 -0.14 -0.12 -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 -40-200 20406080 temperature (oc) v ref error (%) figure 61. typical v ref drift, AD9271-50
preliminary technical data AD9271 rev. pra | page 35 of 58 serial port interface (spi) the AD9271 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. this offers the user added flexibility and customization depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided down into fields, as doc- umented in the memory map section. detailed operational information can be found in the analog devices, inc., user manual interfacing to high speed adcs via spi . there are three pins that define the serial port interface, or spi, to this particular adc. they are the sclk, sdio, and csb pins. the sclk (serial clock) is used to synchronize the read and write data presented to the adc. the sdio (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal adc memory map registers. the csb (chip select bar) is an active low control that enables or disables the read and write cycles (see table 14). table 14. serial port pins pin function sclk serial clock. the serial shift clock input. sclk is used to synchronize serial interface reads and writes. sdio serial data input/output. a dual-purpose pin. the typical role for this pin is as an input or output, depending on the instruction sent and the relative position in the timing frame. csb chip select bar (active low). this control gates the read and write cycles. the falling edge of the csb in conjunction with the rising edge of the sclk determines the start of the framing sequence. during an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, whic h is determined by bit fields w0 and w1. an example of the serial timing and its definitions can be found in figure 63 and table 15. in normal operation, csb is used to signal to the device that spi commands are to be received and processed. when csb is brought low, the device processes sclk and sdio to process instructions. normally, csb remains low until the comm unication cycle is complete. however, if connected to a slow device, csb can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. csb can be stalled when transferring one, two, or three bytes of data. when w0 and w1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until the csb is taken high to end the communication cycle. this allows complete memory transfers without having to provide additional instructions. regardless of the mode, if csb is taken high in the middle of any byte transfer, the spi state machine is reset and the device waits for a new instruction. in addition to the operation modes, the spi port can be configured to operate in different manners. for applications that do not require a control port, the csb line can be tied and held high. this places the remainder of the spi pins in their secondary mode as defined in the serial port interface (spi) section. csb can also be tied lo w to enable 2-wire mode. when csb is tied low, sclk and sdio are the only pins required for communication. although the device is synchronized during power-up, caution must be exerci sed when using this mode to ensure that the serial port re mains synchronized with the csb line. when operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. without an active csb line, streaming mode can be entered but not exited. in addition to word length, the instruction phase determines if the serial frame is a read or writ e operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. if the instruction is a readback operation, performing a readback causes the serial data input/output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb- or lsb-first mode. msb-first mode is the default at power-up and can be changed by adjusting the configuration register. for more information about this and other features, see the user manual interfacing to high speed adcs via spi . hardware interface the pins described in table 14 compose the physical interface between the users programming device and the serial port of the AD9271. the sclk and csb pins function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. in cases where multiple sdio pins share a common connection, care should be taken to ensure that proper v oh levels are met. figure 62 shows the number of sdio pins that can be connected together, assuming the same load as the AD9271 and the resulting v oh level. 05967-037 number of sdio pins connected together voh 1.715 1.720 1.725 1.730 1.735 1.740 1.745 1.750 1.755 1.760 1.765 1.770 1.775 1.780 1.785 1.790 1.795 1.800 030 20 10 40 50 60 70 80 90 100 figure 62. sdio pin loading
AD9271 preliminary technical data rev. pra | page 36 of 58 this interface is flexible enough to be controlled by either serial proms or pic mirocontrollers. this provides the user an alternative method, other than a full spi controller, to program the adc (see the an-812 application note). if the user chooses not to use the spi interface, these pins serve a dual function and are associated with secondary functions when the csb is strapped to avdd during device power-up. see the section for details on which pin-strappable functions are supported on the spi pins. don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t hi t clk t lo t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 06304-068 figure 63. serial timing details table 15. serial timing definitions parameter minimum timing (ns) description t ds 5 setup time between the data and the rising edge of sclk t dh 2 hold time between the data and the rising edge of sclk t clk 40 period of the clock t s 5 setup time between csb and sclk t h 2 hold time between csb and sclk t hi 16 minimum period that sclk should be in a logic high state t lo 16 minimum period that sclk should be in a logic low state t en_sdio 1 minimum time for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 63). t dis_sdio 5 minimum time for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 63).
preliminary technical data AD9271 rev. pra | page 37 of 58 memory map reading the memory map table each row in the memory map table has eight address locations. the memory map is roughly divided into three sections: chip configuration register map (address 0x00 to address 0x02), device index and transfer register map (address 0x05 and address 0xff), and program register map (address 0x08 to address 0x25). the left most column of the memory map indicates the register address number, and the default value is shown in the right most column. the (msb) bit 7 column is the start of the default hexa- decimal value given. for example, address 0x09, clock, has a default value of 0x01, meaning that bit 7 = 0, bit 6 = 0, bit 5 = 0, bit 4 = 0, bit 3 = 0, bit 2 = 0, bit 1 = 0, and bit 0 = 1, or 0000 0001 in binary. this setting is the default for the duty cycle stabilizer in the on condition. by writing a 0 to bit 6 of this address followed by an 0x01 in register 0xff (transfer bit), the duty cycle stabilizer turns off. it is important to follow each writing sequence with a transfer bit to update the spi registers. for more information on this and other functions, consult the user manual interfacing to high speed adcs via spi . reserved locations undefined memory locations should not be written to except when writing the default values suggested in this data sheet. addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. default values after a reset, critical registers are automatically loaded with default values. these values are indicated in table 16, where an x refers to an undefined feature. logic levels an explanation of various registers follows: bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. similarly, clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit.
AD9271 preliminary technical data rev. pra | page 38 of 58 table 16. memory map register addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configuration registers 00 chip_port_config 0 lsb first 1 = on 0 = off (default) soft reset 1 = on 0 = off (default) 1 1 soft reset 1 = on 0 = off (default) lsb first 1 = on 0 = off (default) 0 0x18 the nibbles should be mirrored so that lsb- or msb-first mode registers correctly regardless of shift mode. 01 chip_id chip id bits 7:0 (AD9271 = 0x13), (default) read only default is unique chip id, different for each device. this is a read-only register. 02 chip_grade x x child id 6:4 (identify device variants of chip id) 00 = 50 msps (default) 01 = 40 msps 11 = 25 msps x x x x 0x00 child id used to differentiate graded devices. device index and transfer registers 04 device_index_2 x x x x data channel h 1 = on (default) 0 = off data channel g 1 = on (default) 0 = off data channel f 1 = on (default) 0 = off data channel e 1 = on (default) 0 = off 0x0f bits are set to determine which on-chip device receives the next write command. 05 device_index_1 x x clock channel dco 1 = on 0 = off (default) clock channel fco 1 = on 0 = off (default) data channel d 1 = on (default) 0 = off data channel c 1 = on (default) 0 = off data channel b 1 = on (default) 0 = off data channel a 1 = on (default) 0 = off 0x0f bits are set to determine which on-chip device receives the next write command. ff device_update x x x x x x x sw transfer 1 = on 0 = off (default) 0x00 synchronously transfers data from the master shift register to the slave. adc functions 08 modes x x x x lna bypass 1 = on 0 = off (default) internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset 100 = cw mode (tgc pwdn) 0x00 determines various generic modes of chip operation. 09 clock x x x x x x x duty cycle stabilizer 1 = on (default) 0 = off 0x01 turns the internal duty cycle stabilizer on and off. 0d test_io user test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once reset pn long gen 1 = on 0 = off (default) reset pn short gen 1 = on 0 = off (default) output test modesee table 12 in the digital outputs and timing section 0000 = off (default) 0001 = midscale short 0010 = +fs short 0011 = ?fs short 0100 = checkerboard output 0101 = pn 23 sequence 0110 = pn 9 0111 = one/zero word toggle 1000 = user input 1001 = one/zero bit toggle 0x00 when set, the test data is placed on the output pins in place of normal data. (local, expect for pn sequence)
preliminary technical data AD9271 rev. pra | page 39 of 58 addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) 0f flex_channel_input filter cutoff frequency control 0000 = 0.7 1/3 f sample 0001 = 0.8 1/3 f sample 0010 = 0.9 1/3 f sample 0011 = 1.0 1/3 f sample 0100 = 1.1 1/3 f sample 0101 = 1.2 1/3 f sample 0110 = 1.3 1/3 f sample x x x x 0x30 antialiasing filter cutoff (global) 10 flex_offset x x 6-bit lna offset adjustment table = tbd 0x20 lna force offset correction (local) 11 flex_gain x x x x x x lna gain 00 = 5 01 = 6 10 = 8 0x01 lna gain adjustment (global) 14 output_mode x 0 = lvds ansi (default) 1 = lvds low power, (ieee 1596.3 similar) x x x output invert 1 = on 0 = off (default) 00 = offset binary (default) 01 = twos complement 0x00 configures the outputs and the format of the data. 15 output_adjust x x output driver termination 00 = none (default) 01 = 200 10 = 100 11 = 100 x x x dco and fco 2 drive strength 1 = on 0 = off (default) 0x00 determines lvds or other output properties. primarily functions to set the lvds span and common-mode levels in place of an external resistor. 16 output_phase x x x x 0011 = output clock phase adjust (0000 through 1010) (default: 180 relative to data edge) 0000 = 0 relative to data edge 0001 = 60 relative to data edge 0010 = 120 relative to data edge 0011 = 180 relative to data edge 0100 = 240 relative to data edge 0101 = 300 relative to data edge 0110 = 360 relative to data edge 0111 = 420 relative to data edge 1000 = 480 relative to data edge 1001 = 540 relative to data edge 1010 = 600 relative to data edge 1011 to 1111 = 660 relative to data edge 0x03 on devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. internal latching is unaffected. 19 user_patt1_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user-defined pattern, 1 lsb (global). 1a user_patt1_msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user-defined pattern, 1 msb (global). 1b user_patt2_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user-defined pattern, 2 lsb. (global) 1c user_patt2_msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user-defined pattern, 2 msb (global).
AD9271 preliminary technical data rev. pra | page 40 of 58 addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 21 serial_contr ol lsb first 1 = on 0 = off (default) x x x <10 msps, low encode rate mode 1 = on 0 = off (default) 000 = 12 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits 0x00 serial stream control. default causes msb first and the native bit stream (global). 22 serial_ch_stat x x x x x x channel output reset 1 = on 0 = off (default) channel power- down 1 = on 0 = off (default) 0x00 used to power down individual sections of a converter (local). 2b flex_filter x enable automatic low-pass tuning 1 = on 0 = off (default) x x x x high-pass filter cutoff 00 = dc (default) 01 = 700 khz 10 = 350 khz 0x00 filter cutoff (global) 2c analog_input x x x x x x x losw 1 = on 0 = off (default) 0x00 lna active termination/input impedance (global) 2d cross_point_switch x x x crosspoint switch enable 0 0000 = cdw0p/n 0 0001 = cdw1p/n 0 0010 = cdw2p/n 0 0011 = cdw3p/n 0 0100 = cdw4p/n 0 0101 = cdw5p/n 0 0111 = power down cw channel 1 0000 = cdw0p se 1 0001 = cdw1p se 1 0010 = cdw2p se 1 0011 = cdw3p se 1 0100 = cdw4p se 1 0101 = cdw5p se 1 0111 = power down cw channel 1 1000 = cdw0n se 1 1001 = cdw1n se 1 1010 = cdw2n se 1 1011 = cdw3n se 1 1100 = cdw4n se 1 1101 = cdw5n se 1 1111 = power down cw channel 0x07 crosspoint switch enable (local)
preliminary technical data AD9271 rev. pra | page 41 of 58 power and ground recommendations when connecting power to the AD9271, it is recommended that two separate 1.8 v supplies be used: one for analog (avdd) and one for digital (drvdd). the AD9271 also requires a 3.3 v supply (cwvdd) as well for the crosspoint section. if only one 1.8 v supply is available, it should be routed to the avdd first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the drvdd. the user should employ several decoupling capacitors on all supplies to cover both high and low frequencies. these should be located close to the point of entry at the pc board level and close to the parts with minimal trace lengths. a single pc board ground plane should be sufficient when using the AD9271. with proper decoupling and smart parti- tioning of the pc boards analog, digital, and clock sections, optimum performance is easily achieved. exposed paddle thermal heat slug recommendations it is required that the exposed paddle on the underside of the adc is connected to analog ground (agnd) to achieve the best electrical and thermal performance of the AD9271. an exposed continuous copper plane on the pcb should mate to the AD9271 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be solder filled or plugged. to maximize the coverage and adhesion between the adc and pcb, partition the continuous copper plane by overlaying a silk- screen on the pcb into several uniform sections. this provides several tie points between the two during the reflow process. using one continuous plane with no partitions only guarantees one tie point between the AD9271 and pcb. see figure 64 for a pcb layout example. for more detailed information on packaging and the pcb layout, see the an-772 application note . silkscreen p a rtition pin 1 indicator 06304-069 figure 64. typical pcb layout
AD9271 preliminary technical data rev. pra | page 42 of 58 evaluation board the AD9271 evaluation board provides all of the support circuitry required to operate the adc in its various modes and configur- ations. the lna is driven differentially through a transformer. figure 65 shows the typical bench characterization setup used to evaluate the ac performance of the AD9271. it is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the signal chain. proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. see figure x to figure x for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level. power supplies this evaluation board comes with a wall-mountable switching power supply that provides a 6 v, 2 a maximum output. simply connect the supply to the rated 100 v ac to 240 v ac wall outlet at 47 hz to 63 hz. the other end is a 2.1 mm inner diameter jack that connects to the pcb at p701. once on the pc board, the 6 v supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board. when operating the evaluation board in a nondefault condition, l702 to l704 can be removed to disconnect the switching power supply. this enables the user to bias each section of the board individually. use p501 to connect a different supply for each section. at least one 1.8 v supply is needed with a 1 a current capability for avdd_dut and drvdd_dut; however, it is recommended that separate supplies be used for both analog and digital domains. to operate the evaluation board using the spi and alternate clock options, a separate 3.3 v analog supply is needed in addition to the other supplies. the 3.3 v supply, or avdd_3.3 v, should have a 1 a current capability. to bias the crosspoint switch circuitry or cw section, separate +5 v and ?5 v supplies are required. these should have 1 a current capability each. this section cannot be biased from a 6 v, 2 a wall supply. separate supplies are required. input signals when connecting the clock and analog source, use clean signal generators with low phase noise, such as rohde & schwarz smhu or hp8644 signal generators or the equivalent. use a 1 m, shielded, rg-58, 50 coaxial cable for making connections to the evalu- ation board. enter the desired frequency and amplitude from the specifications tables. the evaluation board is set up to be clocked from the crystal oscillator, osc401. if a different or external clock source is desired, follow the instructions for clock outlined in the default operation and jumper selection settings section. typically, most analog devices evaluation boards can accept ~2.8 v p-p or 13 dbm sine wave input for the clock. when connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 terminations. analog devices uses tte and k&l microwave, inc., band-pass filters. the filter should be connected directly to the evaluation board. output signals the default setup uses the hsc-adc-fpga-8 high speed deserialization board to deserialize the digital output data and convert it to parallel cmos. these two channels interface directly with the analog devices standard dual-channel fifo data capture board (hsc-adc-evalb-dc). two of the eight channels can then be evaluated at the same time. for more information on channel settings on these boards and their optional settings, visit www.analog.com/fifo. rohde & schwarz, smhu, 2v p-p signal synthesizer rohde & schwarz, fs5a20 spectrum analyzer band-pass filter cha to chh 12-bit serial lvds 2 ch 12-bit parallel cmos usb connection AD9271 hsc-adc-fpga-8 high speed deserialization board hsc-adc-evalb-dc fifo data capture board pc running adc analyzer and spi user software 1.8v ?+ ?+ avdd_dut avdd_3.3v drvdd_dut gnd gnd 1.8v 6v dc 2a max vfac3 oscillator wall outlet 100v to 240v ac 47hz to 63hz switching power supply ?+ gnd 3.3v ?+ 1.5v_fpga 3.3v_d gnd 3.3v ?+ gnd 1.5v ?+ vcc gnd 3.3v spi spi spi spi 0 6304-070 analog input cw output clk evaluation board figure 65. evaluation board connection
preliminary technical data AD9271 rev. pra | page 43 of 58 default operation and jumper selection settings the following is a list of the default and optional settings or modes allowed on the AD9271 rev. a evaluation board. ? power: connect the switching power supply that is supplied in the evaluation kit between a rated 100 v ac to 240 v ac wall outlet at 47 hz to 63 hz and p701. ? ain: the evaluation board is set up for a transformer- coupled analog input with optimum 50 impedance matching out to 18 mhz (see figure 66). for a different bandwidth response, change the 22 pf capacitor at the lna (li-x) analog input. figure 66. evaluation bo ard full power bandwidth ? vref: vref is set to 1.0 v by tying the sense pin to ground, r317. this causes the adc to operate in 2.0 v p-p full-scale range. a separate external reference option using the adr510 or adr520 is also included on the evaluation board. populate r311 and r315 with 0 resistors and remove c307. proper use of the vref options is noted in the voltage reference section. ? rbias: rbias has a default setting of 10 k (r301) to ground and is used to set the adc core bias current. to further lower the core power (excluding the lvds driver supply), change the resistor setting. however, performance of the adc may degrade depending on the resistor chosen. see rbias section for more information. ? clock: the default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (t401) that adds a very low amount of jitter to the clock path. the clock input is 50 terminated and ac-coupled to handle single-ended sine wave types of inputs. the transformer converts the single-ended input to a differential signal that is clipped before entering the adc clock inputs. the evaluation board is already set up to be clocked from the crystal oscillator, osc401. this oscillator is a low phase noise oscillator from valpey fisher (vfac3-bhl-50mhz). if a different clock source is desired, remove r403, set jumper j401 to disable the oscillator from running, and connect the external clock source to the sma connector, p401. a differential lvpecl clock driver can also be used to clock the adc input using the ad9515 (u401). populate r406 and r407 with 0 resistors and remove r415 and r416 to disconnect the default clock path inputs. in addition, populate c405 and c406 with a 0.1 f capacitor and remove c409 and c410 to disconnect the default cloth path outputs. the ad9515 has many pin-strappable options that are set to a default mode of operation. consult the ad9515 data sheet for more information about these and other options. ? pdwn: to enable the power-down feature, short p303 to the on position (avdd) on the pdwn pin. ? stdby: to enable the standby feature, simply short p302 to the on position (avdd) on the stdby pin. ? gain: to change the gain on the vga, drive these pins from 0 v to 1 v on j301. this changes the vga gain from 0 db to 30 db. this feature can also be driven from the r335 and r336 on-board resistive dividers by installing a 0 resistor in r337. ? non-spi mode: for users who wish to operate the dut without using spi, remove the jumpers on j501. this disconnects the csb, sclk, and sdio pins from the control bus, allowing the dut to operate in its simplest mode. each of these pins has internal termination and will float to its respective level. note that the device will only work in its default condition. ? cwd+,cwd?: to view muiltple cw outputs, jumper together the appropriate outputs on p403 and p404. all outputs are summed together on iop and ion buses, fed to a 1:4 impedance ratio transformer, and buffered so that the user can view the output on a spectrum analyzer. this can be configured to be viewed in single-ended mode (default) or in differential mode. to set the voltage for the appropriate number of channels to be summed, change the value of r447 and r448 on the primary transformer (t402). ? d+, d?: if an alternative data capture method to the setup described in figure 67 is used, optional receiver terminations, r318, r320 to r330, can be installed next to the high speed backplane connector.
AD9271 preliminary technical data rev. pra | page 44 of 58 ain cha ain chb ain chd ain chc 0 r13 0 r151 0 r153 0 0 r152 0 r102 r13 6 0-dn p c116 0.1uf-dn p c115 0.1uf c113 0.1uf r157 0-dn p 50-dn p r128 0-dn p r12 7 0.1uf-dn p c112 0.1uf c111 0.1uf c109 0-dn p r15 6 r119 50-dn p 0-dn p r118 0.1uf-dn p c108 0.1uf c107 0.1uf c105 0-dn p r155 r110 50-dn p 50-dn p r101 r154 0-dn p c101 0.1uf r109 0-dn p c104 0.1uf-dn p c103 0.1uf 0.1uf c121 lid 0.1uf c124 lg d 50 r160 lgc li c c123 0.1uf r158 50 c122 0.1uf lia lga ctd 3 52 4 1 6 adt1-1w t t10 4 ctd ct c 3 52 4 1 6 adt1-1w t t10 3 ct c ct b ct b ct a 6 14 2 5 3 t10 1 adt1-1w t ct a 3 52 4 1 6 adt1-1w t t10 2 gnd d gnd c gnd b gnd a 10k-dn p r147 1 r145 10k-dn p 1 r143 10k-dn p 1 10k-dn p r141 0-dn p r149 r150 0-dn p r137 0-dn p 200 r126 c10 2 22p f 1 avdd_du t lo- a r106 0 r142 10k-dn p 0.1uf-dn p c11 7 j10 1 r10 8 200 1k-dn p r10 7 losw a lgb lib losw b 1k-dn p r11 6 200 r11 7 j10 2 c118 0.1uf-dn p 10k-dn p r144 r111 0-dn p 0 r115 avdd_du t 22p f c10 6 lo- b losw c r12 5 1k-dn p j10 3 c119 0.1uf-dn p 10k-dn p r146 r103 0-dn p 0 r124 lo- c avdd_du t 22p f c110 c114 22p f avdd_du t lo- d r133 0 0-dn p r129 r148 10k-dn p 0.1uf-dn p c120 j10 4 r135 200 1k-dn p r134 losw d 0-dn p r112 0-dn p r104 r138 0-dn p r131 0-dn p r122 0-dn p 0-dn p r140 0-dn p r121 0-dn p r113 r139 0-dn p 50 r159 r161 50 06304-086 figure 67. evaluation board schematic, dut analog inputs
preliminary technical data AD9271 rev. pra | page 45 of 58 a in che ain chf ain chg ain chh 0 r25 2 0 r25 1 0 r25 0 0 r24 9 c21 6 0.1uf-dn p r23 6 0-dn p c21 5 0.1uf c21 3 0.1uf r25 7 0-dn p 50-dn p r22 8 0-dn p r22 7 0.1uf-dn p c21 2 0.1uf c21 1 0.1uf c20 9 0-dn p r25 6 r21 9 50-dn p c20 8 0.1uf-dn p r21 8 0-dn p c20 7 0.1uf c20 5 0.1uf r25 5 0-dn p 50-dn p r21 0 0.1uf-dn p c20 4 0-dn p r20 9 0.1uf c20 3 0.1uf c20 1 0-dn p r25 4 r20 1 50-dn p 0.1uf c22 4 c22 3 0.1uf c22 2 0.1uf r25 8 50 0.1uf c22 1 lge lie 1 cth cth 6 14 2 5 3 t202 adt1-1w t ctg 6 14 2 5 3 t20 3 adt1-1w t ctg ct f ctf cte 6 14 2 5 3 t201 adt1-1w t cte 6 14 2 5 3 t20 4 adt1-1w t gnd h gnd g gnd f gnd e r20 4 10k-dn p 1 1 1 r21 1 0-dn p j20 2 0.1uf-dn p c22 0 22p f c21 0 200 r22 6 r22 5 1k-dn p 1k-dn p r21 6 r20 8 200 c20 2 22p f avdd_du t 10k-dn p r24 2 lo- e r20 6 0 0-dn p r20 2 r24 3 10k-dn p 0.1uf-dn p c21 7 j20 1 1k-dn p r20 7 losw e lg f li f losw f 200 r21 7 c21 8 0.1uf-dn p 10k-dn p r24 4 0 r21 5 avdd_du t 22p f c20 6 lo- f lgg lig losw g j20 3 c21 9 0.1uf-dn p 10k-dn p r24 6 r21 3 0-dn p 0 r22 4 lo- g r24 5 10k-dn p avdd_du t c21 4 22p f avdd_du t 10k-dn p r24 7 lo- h r23 3 0 0-dn p r22 9 r24 8 10k-dn p j20 4 r23 5 200 1k-dn p r23 4 losw h li h lg h r20 3 0-dn p 0-dn p r21 2 0-dn p r22 1 0-dn p r23 8 r22 2 0-dn p r23 0 0-dn p r23 9 0-dn p 0-dn p r23 1 0-dn p r23 7 0-dn p r24 0 r24 1 0-dn p r25 3 0-dn p 50 r25 9 r26 0 50 50 r26 1 06304-087 figure 68. evaluation board schematic, dut analog inputs (continued)
AD9271 preliminary technical data rev. pra | page 46 of 58 avdd a avdd b avdd c avdd d avdd e avddf avdd g avddh clk + clk - csb cvdd cwd0+ cwd0 - cwd1+ cwd1 - cwd2+ cwd2 - cwd3+ cwd3 - cwd4+ cwd4 - cwd5+ cwd5 - cwvdd d+ a d+ b d+ c d+d d+e d+f d+g d+h d-a d-b d-c d-d d-e d-f d-g d-h dco + dco- drvd d dvdd fco+ fco- gain+ gain - lga lgb lgc lgd lge lgf lgg lgh lia lib li c lid lie li f lig lih lo-a lo-b lo- c lo- d lo- e lo- f lo- g lo- h losw a losw b losw c losw d losw f losw g losw h pwdn ravd d ref t sense rbia s scl k sdi o ref b stdby vref losw e pad avdd e avddf avdd g avddh drvd d avdd c avdd d avdd a avdd b gnd vout trim/nc a1 a1 0 a2 a3 a4 a5 a6 a7 a8 a9 b1 b1 0 b2 b3 b4 b5 b6 b7 b8 b9 c1 c1 0 c2 c3 c4 c5 c6 c7 c8 c9 d1 d1 0 d2 d3 d4 d5 d6 d7 d8 d9 gndab 1 gndab1 0 gndab 2 gndab 3 gndab 4 gndab 5 gndab 6 gndab 7 gndab 8 gndab 9 gn dcd 1 gndcd1 0 gn dcd 2 gn dcd 3 gn dcd 4 gn dcd 5 gn dcd 6 gn dcd 7 gn dcd 8 gn dcd 9 cw cw referenc e decoupling using external vre f vref=1 v vref = externa l 1v optional ext ref nc referencecircuitry r205-r21 0 optional outpu t termination s vref selec t remove c307 whe n vref=0.5v(1+r313/r312 ) gain dri v einp u t digital outputs avdd_du t 0-dn p r33 7 in r33 1 100-dn p ggn d 100-dn p r30 4 r31 0 10k-dn p r33 6 10 k 100-dn p r33 0 1 10 2 3 4 5 6 7 8 9 11 20 12 13 14 15 16 17 18 19 31 40 32 33 34 35 36 37 38 39 41 50 42 43 44 45 46 47 48 49 21 30 22 23 24 25 26 27 28 29 51 60 52 53 54 55 56 57 58 59 p3 0 1 0.1u f c30 9 c30 8 0.1u f r30 3 10 0 j30 1 c301 0.1u f 0.1uf c30 5 1k r30 9 ad r510_2 0 u30 2 470k-dn p r30 8 10 16 22 26 4 54 60 66 72 55 61 67 73 3 9 15 21 24 23 53 25 79 78 81 80 83 82 94 93 96 95 98 97 84 46 44 42 40 34 32 30 28 45 43 41 39 33 31 29 27 36 35 47 50 38 37 86 85 56 62 68 74 2 8 14 20 57 63 69 75 1 7 13 19 59 65 71 77 99 5 11 17 58 64 70 76 6 12 18 49 92 91 88 87 51 52 90 48 89 100 101 u301 AD9271 1u f c30 7 0.1uf c30 6 dn p r31 5 4.7uf c302 10k r301 r33 8 10 k avdd_du t 1k r32 5 2 1 berg69157-10 2 p302 r335 8k avdd_du t 1 2 p303 berg69157-10 2 sclk_du t sdio_du t c304 0.1u f 0-dn p r31 1 ch b r32 9 100-dn p 100-dn p r32 8 r32 7 100-dn p 100-dn p r32 4 r32 3 100-dn p 100-dn p r31 8 r32 0 100-dn p r32 1 100-dn p r32 2 100-dn p r31 9 1k dn p r31 2 dn p r31 6 0 r31 7 vsense_du t vref_du t vsense_du t 0.1u f c303 1k r32 6 cwd1 - lo- d ch d ch d avdd_cha avdd_dut drvdd_du t clk avdd_ch h avdd_ch e cwd2+ cwd3 - sdo_ch b lo- h losw h lih lgh dn p r31 3 avdd_du t avdd_du t csb4_ch b fc o ch a ch b fc o ch a ch c dc o dc o ch c sclk_ch b sclk_ch a sdi_cha csb1_ch a sdo_ch a sdi_ch b csb2_ch a csb3_ch b ch b chc chd ch b chc chd dc o dc o fco fco chg chg chf chf che che clk cwd3+ cwd4 - cwd4+ cwd5 - cwd5+ lo- e losw e cwd2 - lga lia losw a lo-a lgb lib losw b lo-b lgc li c losw c lo- c lgd lid cwd1+ losw d lie lge lo- f losw f li f lgf lo- g losw g lig lgg chh chh ch a ch a avdd_dut avdd_3.3 v avdd_chf avdd_ch g avdd_du t drvdd_du t avdd_chb avdd_chc avdd_ch d che che chf chf chg chg chh chh cwd0+ cwd0 - vref_du t csb_dut 50 r30 2 avdd_du t r30 5 0-dn p 0 6304-088 figure 69. evaluation board schematic, dut, vref, and digital output interface
preliminary technical data AD9271 rev. pra | page 47 of 58 clk clkb gnd gnd_pa d out0 out0b out1 out1b rset s0 s1 s10 s2 s3 s4 s5 s6 s7 s8 s9 syncb vref vs signal=dnc;27,2 8 oe gnd out vcc cw doppler circuitry dnp dnp dnp dnp dnp inpu t encod e enc enc clock circuit dnp dnp dnp dnp dnp optional clock oscillator ad9515 pin-strap setting s optional clock drive circuit clipsineout (default ) dnp lvpecloutpu t lvds outpu t aout aout enable osc201 disableosc201 dn p 0-dn p r46 2 r46 0 0-dn p -5v cwd2 cwd1 cwd2 r46 4 0-dn p 0-dn p r45 9 r46 1 0-dn p 0-dn p r44 9 r46 6 0-dn p ad812ar r45 0 0 c40 3 0.1uf 0.1uf c40 2 opt_clk p402 10 12 3 5 opt_clk 50-dn p r41 1 +5v 3 52 4 1 6 adt1-1wt t401 0 r40 3 r42 2 100 c419 0.1uf c40 5 0.1uf-dn p 10 k r41 3 12 6 7 25 8 16 9 15 10 14 11 13 3 2 5 18 19 23 22 32 1 31 33 u401 signal=avdd_3.3v;4,17,20,21,24,26,29,3 0 ad9515 r40 9 dn p r41 4 4.12 k dn p r40 8 0.1uf c422 0 r424 r425 0 p401 j403 j402 43 61 2 5 t402 adtt4-1 c411 0.1uf r42 1 240 50 r40 4 r40 5 0 0.1uf c421 r45 4 750 750 r45 3 ion 125 r44 7 r44 8 125 iop r45 2 0 0-dnp r406 r407 0-dnp r41 2 dn p r40 1 10 k c413 0.1uf 0 r416 0 r41 5 r417 0 r418 0 0.1uf-dn p c40 7 0.1uf-dn p c40 6 r45 1 0 avdd_3.3v 0 r44 6 clk c409 0.1uf c410 0.1uf clk 0.1uf c420 c401 0.1uf 12 11 10 9 8 7 6 5 4 3 2 1 p403 1 2 3 4 5 6 7 8 9 10 11 12 p404 1 3 r427 0 0 r426 s0 0 r436 r437 0 0.1uf c412 c415 0.1uf 0.1uf c416 10 k r40 2 0 r434 c40 8 0.1uf-dn p r444 0 0 r442 r440 0 0 r438 r432 0 0 r430 r428 0 0 r445 r443 0 0 r441 r439 0 r435 0 0 r433 r431 0 0 r429 s4 s5 s3 s2 s1 avdd_3.3v 240 r42 0 r41 0 10 k 100 r42 3 avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v avdd_3.3v s6 s7 s8 s9 s10 0.1uf c414 c418 0.1uf 0.1uf c417 avdd_3.3v avdd_3.3 v avdd_3.3v clk clk avdd_3.3v opt_clk opt_clk s10s9 s8s7s6s5 s4s3s2s1 s0 avdd_3.3v 1 cwd5- cwd3- cwd2- cwd1- cwd0- ion cwd4- cwd5+ cwd3+ cwd1+ cwd0+ cwd2+ iop cwd4+ 0 r46 5 50 r45 5 50 r45 8 0-dn p r46 3 cwd1 06304-089 figure 70. evaluation board schemati c, clock and cw doppler circuitry
AD9271 preliminary technical data rev. pra | page 48 of 58 y1 vcc y2 a2 gnd a1 con00 5 7.5vpowe r 2.5mm jack 2a gnd input output1 output4 gnd input output1 output4 gnd input output1 output4 smdc110f y1 vcc y2 a2 gnd a1 bias psg cb cg cg cg inpu t power supply inp u t inpu t 6v, 2a ma x d np: do not populat e +1.8 v +1.8 v +3.3 v optional powe r +/- 5v power decoupling capacitor s gn d test point s spi circuitry from fifo 2a d702 d703 2a 1 1 1 3 2 4 5 6 l70 1 flthmuratabnx01 6 1 2 34 5 6 nc7wz0 7 u702 1 2 3 p511 weilandz5.531.3325. 0 f701 4 2 3 1 ad p33339akc-3. 3 u70 5 1 32 4 u70 7 ad p33339akc-1. 8 1 32 4 u70 4 ad p33339akc-1. 8 c71 7 1u f 0.1uf c50 2 10u f c50 1 1 2 3 4 5 6 p501 avdd_dut dut_drvd d dut_avd d pwr_in d705 2a 2a d704 d701 pwr_out 1 2 p502 berg69157-10 2 r71 6 240 10 k r71 4 sdo_cha sdi_cha sclk_cha csb1_cha 1 3 2 p70 1 c704 10uf cr702 green c71 4 1u f avdd_dut avdd_ch a avdd_ch c avdd_ch d avdd_ch e avdd_ch f avdd_ch g avdd_ch h 0.1uf c73 0 avdd_ch b drvdd_du t avdd_du t avd d _3.3 v avdd_chh avdd_chg avdd_ch f avdd_che avdd_chd avdd_ch c avdd_ch b avdd_ch a 2 1 berg69157-10 2 p507 10u h l70 3 l70 4 10u h 10u f c71 1 0.1uf c74 1 6 5 4 3 2 1 u703 nc7wz1 6 1k r71 3 0.1uf c74 2 0.1uf c74 0 l70 2 10u h c71 0 0.1uf c70 9 10u f 10u h l70 5 10u h l70 6 c71 5 1u f 0.1uf c70 8 0.1uf c71 2 c71 6 1u f pwr_ou t p wr_o u t 10u f c70 7 dut_avd d dut_drvd d 0.1uf c73 5 0.1uf c73 4 0.1uf c73 3 0.1uf c73 2 0.1uf c73 1 0.1uf c74 3 3.3v_avd d pwr_i n 1u f c71 9 1u f c72 0 l70 7 10u h drvdd_du t 1k r71 2 1k r71 0 r71 5 10 k 10 k r71 1 0.1uf c703 c702 0.1uf avdd_du t avdd_du t sclk_dut csb_du t avdd_3.3v avdd_dut sdio_dut 0.1uf c74 4 0.1uf c74 8 0.1uf c74 7 0.1uf c74 6 0.1uf c74 5 c75 1 0.1uf avdd_3.3v 3.3v_avd d 2 1 berg69157-10 2 p503 1 2 p504 berg69157-10 2 2 1 berg69157-10 2 p505 1 2 p506 berg69157-10 2 1 2 p508 berg69157-10 2 2 1 berg69157-10 2 p509 1 1 l50 1 10u h +5 v 10u h l50 2 -5 v c50 3 10u f c50 4 0.1uf 1 1 1 1 06304-090 figure 71. evaluation board schematic, powe r supply inputs and spi interface circuitry
preliminary technical data AD9271 rev. pra | page 49 of 58 0 6304-081 figure 72. evaluation board layout, top side 06304-082 figure 73. evaluation board layout, ground plane (layer 2)
AD9271 preliminary technical data rev. pra | page 50 of 58 06304-083 figure 74. evaluation board layout, power plane (layer 3) 0 6304-084 figure 75. evaluation board layout, power plane (layer4)
preliminary technical data AD9271 rev. pra | page 51 of 58 06304-085 figure 76. evaluation board layout, ground plane (layer 5) 06304-080 figure 77. evaluation board layout, bottom side
AD9271 preliminary technical data rev. pra | page 52 of 58 table 17. evaluation board bill of materials (bom) 1 item qnty. per board refdes device pkg. value mfg. mfg. part number 1 1 AD9271bsvz_revc pcb pcb pcb 2 71 c101, c103, c105, c107, c109, c111, c113, c115, c121 to c124, c201, c203, c205, c207, c209, c211, c213, c215, c221 to c224, c301, c303 to c306, c308 to c309, c401 to c403, c409 to c422, c502, c504, c702 to c703, c708, c710, c712, c730 to c735, c740 to c748, c751 capacitor c0402 0.1 f 10 v ceramic x5r 0402 panasonic ecj-0eb1a104k 3 8 c102, c106, c110, c114, c202, c206, c210, c214 capacitor c0402 ceramic 22 pf 5% 50 v np0 0402 avx 04025a220jat2a 4 1 c302 capacitor c0603 ceramic 4.7 f 6.3 v x5r 0603 avx c0603c475k9pactu 5 7 c307, c714 to c717, c719 to c720 capacitor c0603 1 f 6.3 v ceramic x5r 0603 panasonic ecj-1vb0j105k 6 5 c501, c503, c707, c709, c711 capacitor c0603 ceramic 10 f 6.3 v x5r 0603 panasonic ecj-1vb0j106m 7 1 c704 capacitor c6032 10 f, 6032-28, tantalum, 16 v, 10% tol kemet t491c106k016as 8 1 cr401 diode sot23 schottky gp ln 20 ma avago (agilent) hsms-2812-tr1g 9 1 cr702 led led0603 green uss type 0603 4 v, 5 m candela panasonic lnj314g8tra 10 5 d701 to 705 diode smbj rectifier sil 2 a 50 v do-214aa micro commercial co. s2a-tp 11 1 f701 fuse polyswitch 1.10 a reset fuse smd tyco/raychem nanosmdc110f-2 12 13 j101 to j104, j201 to j204, j301, j402 to j403, p401 to p402 connector cnsamtec-sma-j- conn-pcb coax sma end launch samtec/johnson sma-j-p-x-st-em1/ 142-0711-821 13 1 j401 connector cnberg1x3h205ld header, 3-pin, male, single row, straight samtec tsw-103-08-g-s 14 1 j501 connector cnberg2x4h350ld header, 8-pin, male, double row, straight samtec tsw-105-08-t-d
preliminary technical data AD9271 rev. pra | page 53 of 58 item qnty. per board refdes device pkg. value mfg. mfg. part number 15 10 p302 to p303, p502 to p509 connector cnberg69157-102 100 mil header jumper, 2-pin samtec tsw-102-07-g-s 16 2 p403 to p404 connector cnberg2x6h330ld 100 mil header, male, 2 6 double row straight samtec tsw-110-08-g-d/ tsw-106-08-g-d 17 8 l501 to l502, l702 to l707 ferrite bead l1210 bead core 3.2 2.5 1.6 smd 1210, 10 h panasonic exc-cl3225u1 18 1 l701 choke coil filter, bnx016-01, emifil lc block murata bnx016-01 19 1 osc401 oscillator osc14p4_cb3 crystal, dual footprint, see eng valpey fisher vfac3-bhl-50mhz 20 1 p301 connector header, right angle, 2-pair, 25 mm, header assembly tyco/amp 6469169-1 21 1 p701 connector 0.08", pcmt dc power, pc mount switchcraft rapc722x 23 38 r102, r103, r106, r111, r115, r124, r129, r130, r133, r151, r152, r153, r202, r206, r211, r213, r215, r224, r229, r233, r249 r252, r305, r317, r403, r405, r415 to r418, r446, r450 to r452, r465, r466 resistor r0402 0 1/16 w 5% 0402 smd panasonic erj-2ge0r00x 24 8 r108, r117, r126, r135, r208, r217, r226, r235 resistor r0402 200 1/16 w 0.5% 0402 smd yageo america rr0510p-201-d 25 12 r158 to r161, r258 to r261, r302, r404, r455, r458 resistor r0402 49.9 1/16 w 0.5% 0402 smd susumu co. rr0510r-49r9-d 26 9 r301, r338, r401 to r402, r410, r413, r711, r714 to r715 resistor r0402 10 k 1/16 w 5% 0402 smd panasonic erj-2gej103x 27 3 r303, r422 to r423 resistor r0402 100 1/16 w 1% 0402 smd panasonic erj-2rkf1000v 28 1 r308 resistor r0402 470 k 1/16 w 5% 0402 smd panasonic rc0402jr-07470kl 29 7 r309, r319, r325, r326, r710, r712, r713 resistor r0402 1.00 k 1/16 w 1% 0402 smd panasonic erj-2rkf1001x 30 1 r335 resistor r0402 8.06 k 1/16 w 1% 0402 smd yageo rc0402fr-078k06l
AD9271 preliminary technical data rev. pra | page 54 of 58 item qnty. per board refdes device pkg. value mfg. mfg. part number 31 2 r310, r336 potentiometer 3-lead 10 k, one turn, smt murata pva2a103a01r00 32 1 r414 resistor r0402 4.12 k 1/16 w 1% 0402 smd panasonic erj-2rkf4121x 33 3 r420 to r421, r716 resistor r0402 thick film, smt 0402, 240 34 11 r424, r427, r429, r431, r433, r435 to r436, r439, r441, r443, r445 resistor r0201 0.0 1/20 w 5% 0201 smd panasonic erj-1ge0r00c 35 2 r447 to r448 resistor r0402 124 1/16 w 0.1% 0402 smd susumu co. rg10p124bct-nd 36 2 r453 to r454 resistor r0402 750 1/16 w 0.1% 0402 smd susumu co. rg10p750bct-nd 37 9 t101 to t104, t201 to t204, t401 transformer minicd542 xfmr rf mini circuits adt1-1wt 38 1 t402 transformer minickcd637 adtt4-1, cd542 mini circuits adtt4-1 39 1 u301 ic sv-100-3 octal lna/ vga/aaf/adc analog devices AD9271bsvz 40 1 u302 ic sot23 adr510, 1.0 v precision low noise shunt v ref analog devices adr510 41 1 u401 ic lfcsp32-5x5-lp ad9515, clk dist, 32 lfcsp, 5 5 mm analog devices ad9515 42 1 u402 ic so8 ad812ar, dual, current feedback op amp, so8 analog devices ad812ar 43 1 u702 ic sc88 nc7wz07, dual buffer, sc88 fairchild nc7wz07p6x_nl 44 1 u703 ic sc88 nc7wz16p6x, uhs dual buffer, sc88 fairchild nc7wz16p6x_nl 45 2 u704, u707 ic sot223-2 regulator, high accuracy, adp3339akc-1.8, 1.8 v analog devices adp3339akc-1-8 46 1 u705 ic sot223-2 regulator, high accuracy, adp3339akc-3.3, 3.3 v analog devices adp3339akc-3-3
preliminary technical data AD9271 rev. pra | page 55 of 58 item qnty. per board refdes device pkg. value mfg. mfg. part number 47 4 mp101 to mp104 assembly insert into four large holes on corners of board from the bottom side cbsb-14-01, 7/8" height, standoffs for circuit board support, no adhesive richco cbsb-14-01 48 6 mp105 to mp108 assembly place into j502-509 snt-100-bk-g-h, 100 mil jumpers samtec snt-100-bk-g-h 1 this bom is rohs compliant.
AD9271 preliminary technical data rev. pra | page 56 of 58 outline dimensions compliant to jedec standards ms-026-aed-hd 0.27 0.22 0.17 1 25 26 50 76 100 75 51 14.00 bsc sq 16.00 bsc sq 0.50 bsc lead pitch 0.75 0.60 0.45 1.20 max 1 25 26 50 76 100 75 51 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) bottom view (pins up) 9.50 sq exposed pad notes: the package has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full industrial temperature range. the slug is exposed on the bottom of the package and electrically connected to chip ground. it is recommended that no pcb signal traces or vias be located under the package that could come in contact with the conductive slug. attaching the slug to a ground plane will reduce the junction temperature of the device which may be beneficial in high temperature environments. 080706-a figure 78. 100-lead thin quad fl at package, exposed pad [tqfp_ep] (sv-100-3) dimensions shown in millimeters ordering guide model temperature range package description package option AD9271bsvz-50 1 ?40c to +85c 100-lead thin quad flat package, exposed pad [tqfp_ep] sv-100-3 AD9271bsvzrl7-50 1 ?40c to +85c 100-lead thin quad flat packag e, exposed pad [tqfp_ep] tape and reel sv-100-3 AD9271bsvz-40 1 ?40c to +85c 100-lead thin quad flat package, exposed pad [tqfp_ep] sv-100-3 AD9271bsvzrl7-40 1 ?40c to +85c 100-lead thin quad flat packag e, exposed pad [tqfp_ep] tape and reel sv-100-3 AD9271bsvz-25 1 ?40c to +85c 100-lead thin quad flat package, exposed pad [tqfp_ep] sv-100-3 AD9271bsvzrl7-25 1 ?40c to +85c 100-lead thin quad flat packag e, exposed pad [tqfp_ep] tape and reel sv-100-3 AD9271-50ebz 1 evaluation board 1 z = pb-free part.
preliminary technical data AD9271 rev. pra | page 57 of 58 notes
AD9271 preliminary technical data rev. pra | page 58 of 58 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr06304-0-3/07(pra)

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